Senior ASIC Design Engineer - DFX

NVIDIA Corporation; Santa Clara (CA); On-site; USD 190,000 - 310,000; Full time

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Design Engineer - DFX to shape architecture, design, and verification of DFT IP for next‑gen SoCs. You will own fuse controller design, develop scalable DFT methodologies, and collaborate with architecture, design, verification, and backend teams.

The role requires 8+ years in SoC RTL/verification, Verilog, and DFT expertise, plus Python/Perl/Tcl proficiency and post-silicon bring-up experience.

Qualifications

• 8+ years of hands-on experience in SoC architecture, RTL design, and verification.
• Strong proficiency in micro-architecture and RTL development using Verilog (UVM experience is a plus).
• Deep expertise in DFT design, methodology, and implementation.
• Familiarity with clocking, STA, place & route, and power optimization.
• Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.
• Proficiency in scripting languages such as Python, Perl, or Tcl.
• Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges.

Responsibilities

• Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.
• Develop, deploy, and enhance DFT methodologies for scalability and future product needs.
• Define and align feature sets by working closely with architects, platform, and software teams.
• Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
• Create and execute test plans to support both functional and DFT full-chip verification.
• Support post-silicon bring-up and validation efforts including debug and issue resolution.
• Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.

Skills

RTL design

Verification

Verilog

DFT

SoC architecture

Scripting: Python/Perl/Tcl

Post-silicon bring-up

UVM

Education

Bachelors degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

Tools

UVM

Job description

## Senior ASIC Design Engineer - DFXApplylocations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2020883We are now looking for a Senior ASIC Design Engineer - DFX!NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.**What You’ll Be Doing:**As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You’ll help drive innovation across the full silicon lifecycle—from pre-silicon to post-silicon—while mentoring and collaborating with cross-functional teams.Your key responsibilities would include:* Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.* Develop, deploy, and enhance DFT methodologies for scalability and future product needs.* Define and align feature sets by working closely with architects, platform, and software teams.* Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.* Create and execute test plans to support both functional and DFT full-chip verification.* Support post-silicon bring-up and validation efforts including debug and issue resolution.* Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.**What we need to see:*** Bachelors degree (or equivalent experience) with 8+ years of experience, or Master’s degree in Electrical Engineering or related field with 6+ years experience.* 5+ years of hands-on experience in SoC architecture, RTL design, and verification.* Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus.)* Deep expertise in DFT design, methodology, and implementation.* Familiarity with related domains such as clocking, STA, place & route, and power optimization.* Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.* Proficiency in scripting languages such as Python, Perl, or Tcl.* Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges.Why Join Us? This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry’s most complex and impactful semiconductor designs. At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world. You’ll grow alongside world-class engineering teams in a collaborative, fast-paced environment that values innovation, excellence, determination, and teamwork. We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until July 14, 2026.