Lead DFT Methodology Engineer for SoC Test & Verification

Segment (Twilio); Santa Clara (CA); On-site; USD 168,000 - 310,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a DFT Methodology Engineer to drive advanced test access mechanisms, I1149.1/I1500/I1687, memory BIST, and DFX security for multi-million gate SoCs in Santa Clara, CA. You will partner with RTL, timing, physical design, and software teams to shape next-gen products and validate designs through silicon bring-up.

The role requires a Master’s in EE or related field and 10+ years of hands-on experience in DFT, SoC architecture, RTL design, and verification.

Qualifications

• Master’s degree in Electrical Engineering or related field with proven experience in DFT or related domains.
• 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
• Analytical skills in verification and validation of test patterns and logic on complex designs using vendor tools.
• Exposure to RTL & clocks design, STA, place-and-route and power for right trade-offs.
• Experience in silicon debug and bring-up on the ATE with test program development.

Responsibilities

• Own and work with cross-functional teams, implementing state-of-the-art designs in test access mechanisms and DFT architectures.
• Architect, develop and deploy DFT methodologies for next generation products, collaborating with RTL, timing, and physical design teams.
• Mentor junior engineers on test designs and trade-offs including cost and quality.

Skills

DFT engineering

SoC architecture

RTL design

Verification

Test patterns

Education

Master’s degree in Electrical Engineering or related field

Job description

NVIDIA is seeking a DFT Methodology Engineer to drive advanced test access mechanisms, I1149.1/I1500/I1687, memory BIST, and DFX security for multi-million gate SoCs in Santa Clara, CA. You will partner with RTL, timing, physical design, and software teams to shape next-gen products and validate designs through silicon bring-up.

The role requires a Master’s in EE or related field and 10+ years of hands-on experience in DFT, SoC architecture, RTL design, and verification.