Senior DFT Engineer — High-Impact Test & SoC Bring-Up

NVIDIA Corporation

Santa Clara (CA)

On-site

USD 196,000 - 311,000

Full time

7 days ago

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Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Senior DFT Engineer to optimize design tradeoffs and methodology for next-generation CMOS tech. You will lead testing activities, develop patterns, verify designs, and debug complex issues as part of a collaborative team.

The role requires 12+ years in DFT, expertise in IEEE1149.1/IEEE1500, SSN, IOBIST, memory BIST, and strong Python scripting. You will help design packaging vehicles and support optimal product bring-up with ATE, while

Qualifications

BS in Electrical or Computer Engineering or equivalent.
12+ years in Design for Test (DFT).
Knowledge of IEEE1149.1, IEEE1500, SSN scan compression, IOBIST, memory BIST.
Experience in test logic design verification and pattern generation.
ATE test program development and bring-up experience.
Hands-on with industry-standard DFT EDA tools.
Programming/scripting in Python.

Responsibilities

Responsible for all testing aspects: methodology, verification, pattern generation, and debug.
Trade off test time vs data collection to monitor next-gen nodes.
Design and tapeout of advanced packaging vehicles as part of the team.
Assist with root-cause analysis for product bring-up testing issues.