Senior ASIC Design Engineer - DFT

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Job summary

NVIDIA Corporation in Santa Clara, CA, seeks a Senior ASIC Design Engineer to join our DFT team and shape the architecture, design, verification of DFT IPs for next‑generation SoCs.

You will drive DFT methodology, collaborate with cross-functional teams, mentor engineers, and contribute to post-silicon bring-up, with competitive compensation and equity opportunities.

Qualifications

• BS/MS in EE/CE (or equivalent) with 8+ years in SoC architecture, RTL design, and verification.
• Strong Verilog RTL development with micro-architecture focus; UVM a plus.
• Experience in DFT design, methodology, and implementation.
• Familiar with clocking, STA, place & route, and power optimization.
• Post-silicon bring-up on ATE; pattern formats, test development, and failure analysis.
• Scripting: Python, Perl, or Tcl.
• Excellent communication and collaborative mindset; passion for solving complex challenges.

Responsibilities

• Shape architecture, design, implementation, and verification of DFT IPs for next-gen SoCs.
• Lead innovation across full silicon lifecycle from pre-silicon to post-silicon.
• Own fuse controller and other DFT IP architecture and design.
• Develop and enhance DFT methodologies for scalability.
• Define feature sets with architects, platform and software teams.
• Collaborate with design, verification, synthesis, timing, backend teams.
• Create and execute tests for functional and DFT full-chip verification.
• Support post-silicon bring-up and debug, issue resolution.
• Mentor junior engineers on test strategies and trade-offs.

Skills

RTL design

Verilog

UVM

Python

Education

BS/MS Electrical or Computer Engineering

Tools

Python

Job description

We are now looking for a Senior ASIC Design Engineer to join our DFT team!

Make the choice to join us today.

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

• As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products.
• You’ll help drive innovation across the full silicon lifecycle - from pre-silicon to post-silicon - while mentoring and collaborating with cross-functional teams.
• Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs
• Develop, deploy, and enhance DFT methodologies for scalability and future product needs
• Define and align feature sets by working closely with architects, platform, and software teams
• Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration
• Create and execute test plans to support both functional and DFT full-chip verification
• Support post-silicon bring-up and validation efforts including debug and issue resolution
• Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance

What we need to see:

• BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience 8+ years of hands-on experience in SoC architecture, RTL design, and verification
• Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus)
• Experience in DFT design, methodology, and implementation
• Familiarity with related domains such as clocking, STA, place & route, and power optimization
• Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis
• Proficiency in scripting languages such as Python, Perl, or Tcl
• Excellent communication skills and a collaborative mindset - with a curiosity and passion for solving complex technical challenges

Ways to Stand out from the Crowd:

• Experience with UVM-based verification environments
• Experience designing fuse, eFuse, or on-chip security blocks
• Proven track record of successfully architecting DFT IPs across multiple product generations

Why Join Us?

This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry's most complex and impactful semiconductor designs. At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world. You’ll grow alongside world-class engineering teams in a collaborative, fast‑paced environment that values innovation, excellence, determination, and teamwork. We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until September 22, 2026. This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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