Senior ASIC Design Engineer - DFT

engineeringjobs.net, Inc.; Town of Montana (WI); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA seeks a Senior ASIC Design Engineer to join the DFT team in the US. You will own fuse controller and DFT IP design for leading SoC projects, collaborating with architects and backend teams to ensure cohesive integration.

Responsibilities include developing scalable DFT methodologies, supporting post-silicon bring-up, and mentoring junior engineers. Requires 8+ years in SoC RTL/verification, Verilog, and scripting with Python/Perl/Tcl; UVM is a plus.

Qualifications

• BS/MS Electrical or Computer Engineering (or equivalent).
• 8 years of hands-on SoC architecture, RTL design and verification.
• Strong Verilog RTL development; UVM a plus.
• Experience in DFT design, methodology and implementation.
• Familiar with clocking, STA, P&R and power optimization.
• Post-silicon bring-up on ATE; test program development and failure analysis.
• Scripting in Python, Perl or Tcl; strong communication and teamwork.

Responsibilities

• Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.
• Develop, deploy, and enhance DFT methodologies for scalability and future product needs.
• Define and align feature sets by working closely with architects, platform, and software teams.
• Partner with design, verification, synthesis, timing, and backend teams for cohesive integration.
• Create and execute test plans to support functional and DFT full-chip verification.
• Support post-silicon bring-up and validation, including debug and issue resolution.
• Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.

Skills

SoC architecture

RTL design

Verilog

DFT

Python

Perl

Tcl

UVM

Communication

Education

BS/MS Electrical or Computer Engineering (or equivalent)

Tools

UVM

Job description

We are now looking for a Senior ASIC Design Engineer to join our DFT team!

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

• Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs
• Develop, deploy, and enhance DFT methodologies for scalability and future product needs
• Define and align feature sets by working closely with architects, platform, and software teams
• Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration
• Create and execute test plans to support both functional and DFT full-chip verification
• Support post-silicon bring-up and validation efforts including debug and issue resolution
• Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance

What we need to see:

• BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience
• 8 years of hands-on experience in SoC architecture, RTL design, and verification
• Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus)
• Experience in DFT design, methodology, and implementation
• Familiarity with related domains such as clocking, STA, place & route, and power optimization
• Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis
• Proficiency in scripting languages such as Python, Perl, or Tcl
• Excellent communication skills and a collaborative mindset-with a curiosity and passion for solving complex technical challenges

Ways to Stand out from the Crowd:

• Experience with UVM-based verification environments
• Experience designing fuse, eFuse, or on-chip security blocks
• Proven track record of successfully architecting DFT IPs across multiple product generations

Why Join Us?

This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry's most complex and impactful semiconductor designs. At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world. You'll grow alongside world-class engineering teams in a collaborative, fast-paced environment that values innovation, excellence, determination, and teamwork. We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.

#LI-Hybrid

Locations

• US
• CA
• Santa Clara

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 22, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.