Senior AI Chip Architect for LLM Inference ASICs

Acceler8 Talent; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent seeks an experienced Chip Architect to translate architectural concepts into detailed microarchitecture for a next-generation LLM inference ASIC. You will collaborate with RTL, verification, and physical design to ensure architectural decisions become efficient silicon.

You will own critical trade-offs across compute, memory, interconnect, and data movement, optimizing for throughput, latency, power, and area, and influence future silicon generations.

Qualifications

• Extensive ASIC/SoC architecture experience with ownership of hardware design decisions.
• Strong understanding of digital hardware architecture and implementation
• Deep expertise in compute architectures, memory hierarchies, interconnects and data movement.
• Proven ability to translate architectural concepts into implementable microarchitecture.
• Experience evaluating throughput, latency, power, performance and area trade-offs.
• Experience working with RTL, verification and physical design teams.

Responsibilities

• Translate high-level inference requirements into chip and block-level microarchitecture specs.
• Develop and refine architectural decisions across compute, memory, interconnects and data movement.
• Evaluate trade-offs involving throughput, latency, power, performance and area (PPA).
• Collaborate with RTL engineers to translate requirements into hardware implementations.
• Work with design verification and physical design teams to resolve constraints.
• Analyze performance bottlenecks using quantitative data to drive changes.
• Evaluate workload characteristics to optimize inference performance.
• Support first-generation silicon development and tapeout readiness.
• Identify architectural limitations and opportunities for improvement.
• Help define direction for future-generation inference accelerators.

Skills

ASIC/SoC architecture

microarchitecture ownership

RTL impact on architecture

verification collaboration

physical design collaboration

compute architectures

memory hierarchy

interconnects

data movement

PPA trade-offs

Job description

Acceler8 Talent seeks an experienced Chip Architect to translate architectural concepts into detailed microarchitecture for a next-generation LLM inference ASIC. You will collaborate with RTL, verification, and physical design to ensure architectural decisions become efficient silicon.

You will own critical trade-offs across compute, memory, interconnect, and data movement, optimizing for throughput, latency, power, and area, and influence future silicon generations.