Applied AI Engineer for ASIC Design & Verification

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 192,000 - 357,000; Full time

Job summary

NVIDIA seeks a world-class engineer to drive applied research at the intersection of AI and ASIC design. You will apply LLMs, coding agents, and agentic systems to core ASIC problems—RTL generation, verification, and PPA optimization—speeding up design cycles and delivering production-grade results.

This role requires 8+ years in CS/EE with front-end ASIC experience and a proven track record applying agentic AI to chip design.

Qualifications

• MS or PhD or equivalent experience in Computer Science, Electrical/Computer Engineering, or related field.
• 8+ years of proven industry experience.
• Domain and technical expertise in front-end ASIC (design, verification, timing) with project experience applying agentic AI to chip design and optimization.
• Hands-on experience building LLM-based agents or AI tooling used by real users; focus on evaluation and integration.

Responsibilities

• Apply LLMs, coding agents, and agentic systems to core ASIC design problems: RTL generation, design and formal verification, PPA prediction and optimization.
• Build robust data generation and evaluation methodology to separate working systems from demos.
• Wire coding agents into EDA and validation flows to accelerate complex tasks and ramp times.
• Collaborate with NVIDIA's internal Nemotron team to improve models with domain-specific data and post-training.

Skills

Applied AI research

Chip design experience

Front-end ASIC design

Team collaboration

Communication

Evaluation methodology

Education

MS or PhD in CS/EE or related field

Tools

Docker

Slurm

CI/CD

EDA tools

Job description

NVIDIA seeks a world-class engineer to drive applied research at the intersection of AI and ASIC design. You will apply LLMs, coding agents, and agentic systems to core ASIC problems—RTL generation, verification, and PPA optimization—speeding up design cycles and delivering production-grade results.

This role requires 8+ years in CS/EE with front-end ASIC experience and a proven track record applying agentic AI to chip design.