Senior Analog/Mixed-Signal Verilog Modeling Engineer

Broadcom; Irvine (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

401K with company match

Medical, dental, vision benefits

Paid holidays and vacation

Job summary

Broadcom Irvine seeks an experienced engineer to develop Digital-Mixed Signal (DMS) models for analog IPs using SystemVerilog. You will collaborate with analog design and DV teams to verify chip functionality and ensure robust mixed-signal behavior.

The role requires Verilog-AMS expertise, SV UDT/UDR proficiency, and hands-on scripting with TCL/Perl/Python. Experience with Cadence tools and AI-assisted modeling is a plus.

Qualifications

• Bachelor's degree in a relevant field.
• 8+ years of related experience in analog/mixed-signal modeling or verification.
• Strong knowledge of SystemVerilog and Verilog-AMS modeling is required.

Responsibilities

• Develop Digital-Mixed Signal (DMS) models of analog IPs (touch controller AFEs, wireless power charging, health sensing AFE, satellite AFEs) using SystemVerilog.
• Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification.
• Understand Verilog-AMS modeling language.
• Demonstrate proficiency with SystemVerilog UDT/UDR nettype (Cadence wreal or EEnet).
• Familiar with analog circuits (LDOs, TIAs, analog muxing, SARADC S/H, comparators, DAC, buffering).
• Write RTL for digital design and develop testbenches.
• Be fully familiar with SV vs schematic verification for SV models.
• Familiar with Cadence linting & simulation tools (ncsim, xrun, vcs) and analog schematic editor.
• Hands-on scripting in TCL/Perl/Python.
• Experience using AI tools (Cursor, chipAgents) to generate analog SV models and testbenches from design specs.
• Education: Bachelor's degree and 8+ years of related experience.

Skills

SystemVerilog

Verilog-AMS

DMS modeling

Cadence tools

TCL/Perl/Python

AI tools (Cursor, chipAgents)

RTL and testbenches

Analog IP knowledge

Education

Bachelor's degree

Tools

Cadence linting tools

ncsim

xrun

VCS

Analog schematic editor

Job description

Broadcom Irvine seeks an experienced engineer to develop Digital-Mixed Signal (DMS) models for analog IPs using SystemVerilog. You will collaborate with analog design and DV teams to verify chip functionality and ensure robust mixed-signal behavior.

The role requires Verilog-AMS expertise, SV UDT/UDR proficiency, and hands-on scripting with TCL/Perl/Python. Experience with Cadence tools and AI-assisted modeling is a plus.