Senior Analog Modeling Engineer (SystemVerilog/RNM)

PER International; Austin (TX); Hybrid; USD 130,000 - 180,000; Full time

Job summary

PER International in Austin, TX is seeking a Senior Engineer to develop behavioral models for analog and mixed-signal components, enabling efficient design verification and integration between analog IP and digital verification environments.

You’ll work with SystemVerilog, RNM, and SVA, model circuits like LDOs and oscillators, and collaborate across analog, digital, and verification teams in a hybrid setup.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics, or a related field.
• 7+ years of experience in analog/mixed-signal verification or behavioral modeling.
• Strong knowledge of SystemVerilog and Real Number Modeling (RNM).
• Experience with analog blocks (Bandgaps, LDOs, Oscillators, ADCs/DACs).
• Proficiency in Python and effective debugging in simulation environments.
• Ability to work across analog, digital, and verification teams.

Responsibilities

• Develop supply-sensitive and process-aware behavioral models in SystemVerilog for analog and mixed-signal blocks.
• Model circuits including ring oscillators, reference voltage generators, voltage/frequency meters, LDOs, and temperature sensors.
• Perform unit-level verification to validate models against analog design specs.
• Conduct Model vs. Schematic (MvS) verification for comprehensive coverage.
• Debug and resolve analog behavioral modeling issues during system-level simulations.
• Develop SystemVerilog Assertions (SVA) within models to verify controller specifications.
• Collaborate with analog, digital, and verification teams throughout development.

Skills

SystemVerilog

RNM

Analog/mixed-signal verification

Behavioral modeling

Python

SVA / SystemVerilog Assertions

Cadence Virtuoso

VCS

Verdi

Education

Bachelor's degree in Electrical Engineering, Electronics, or related field

Tools

Cadence Virtuoso

VCS

Verdi

Job description

PER International in Austin, TX is seeking a Senior Engineer to develop behavioral models for analog and mixed-signal components, enabling efficient design verification and integration between analog IP and digital verification environments.

You’ll work with SystemVerilog, RNM, and SVA, model circuits like LDOs and oscillators, and collaborate across analog, digital, and verification teams in a hybrid setup.