Analog Modeling Engineer

PER International; Austin (TX); Hybrid; USD 130,000 - 180,000; Full time

Job summary

PER International in Austin, TX is seeking a Senior Engineer to develop behavioral models for analog and mixed-signal components, enabling efficient design verification and integration between analog IP and digital verification environments.

You’ll work with SystemVerilog, RNM, and SVA, model circuits like LDOs and oscillators, and collaborate across analog, digital, and verification teams in a hybrid setup.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics, or a related field.
• 7+ years of experience in analog/mixed-signal verification or behavioral modeling.
• Strong knowledge of SystemVerilog and Real Number Modeling (RNM).
• Experience with analog blocks (Bandgaps, LDOs, Oscillators, ADCs/DACs).
• Proficiency in Python and effective debugging in simulation environments.
• Ability to work across analog, digital, and verification teams.

Responsibilities

• Develop supply-sensitive and process-aware behavioral models in SystemVerilog for analog and mixed-signal blocks.
• Model circuits including ring oscillators, reference voltage generators, voltage/frequency meters, LDOs, and temperature sensors.
• Perform unit-level verification to validate models against analog design specs.
• Conduct Model vs. Schematic (MvS) verification for comprehensive coverage.
• Debug and resolve analog behavioral modeling issues during system-level simulations.
• Develop SystemVerilog Assertions (SVA) within models to verify controller specifications.
• Collaborate with analog, digital, and verification teams throughout development.

Skills

SystemVerilog

RNM

Analog/mixed-signal verification

Behavioral modeling

Python

SVA / SystemVerilog Assertions

Cadence Virtuoso

VCS

Verdi

Education

Bachelor's degree in Electrical Engineering, Electronics, or related field

Tools

Cadence Virtuoso

VCS

Verdi

Job description

Work Setup: Hybrid – Monday to Thursday onsite, Friday remote

About the Company

Our client is a leading global fabless semiconductor company developing advanced, high-performance and power-efficient technologies for a wide range of connected applications.

The company operates at the forefront of areas including AI, wireless connectivity, mobile and computing technologies, with semiconductor solutions used across consumer electronics, smart devices, automotive, high-performance computing and data center applications. Working with major technology brands worldwide, the business offers engineers the opportunity to contribute to advanced semiconductor technologies used across global markets.

Job Summary

In this role, you will develop behavioral models for analog and mixed-signal components, helping enable efficient design verification and integration between analog IP and digital verification environments.

The position is particularly suited to an engineer with strong experience in SystemVerilog, Real Number Modeling (RNM), analog/mixed-signal verification, and behavioral modeling.

Key Responsibilities And Activities Include

• Develop supply-sensitive and process-aware behavioral models in SystemVerilog for analog and mixed-signal blocks.
• Model circuits including ring oscillators, reference voltage generators, voltage/frequency meters, LDOs, and temperature sensors.
• Perform unit-level verification to validate behavioral models against analog design specifications.
• Perform Model vs. Schematic (MvS) verification to ensure model accuracy and achieve comprehensive coverage.
• Debug and resolve analog behavioral modeling issues encountered during system-level digital simulations.
• Develop SystemVerilog Assertions (SVA) within models to verify that digital controllers meet analog specification requirements.
• Work closely with analog design, digital design, and verification teams throughout the development and verification process.

Education And Experience Requirements

• Bachelor's degree in Electrical Engineering, Electronics, or a related field.
• 7+ years of experience in analog/mixed-signal verification or behavioral modeling.
• Strong knowledge of SystemVerilog and Real Number Modeling (RNM).
• Good understanding of analog circuits such as: Bandgaps, LDOs, Oscillators, ADCs / DACs.
• Experience with simulation and debugging environments.
• Proficiency in scripting languages such as Python.
• Strong problem-solving and communication skills.
• Ability to work effectively across analog design, digital design, and verification teams.

Competency requirement

• Experience with mixed-signal design and verification flows.
• Knowledge of analog design environments such as Cadence Virtuoso.
• Understanding of analog-digital integration challenges.
• Knowledge of power and thermal management control circuits.
• Experience with industry-standard simulation and debug tools such as VCS and Verdi is beneficial.

The position offers a competitive compensation and benefits package based on the successful candidate’s skills, experience, and qualifications.

The overall package may include a performance bonus, short- and long-term incentive programs, comprehensive health coverage, life and disability insurance, paid time off, parental leave, retirement benefits, and other employee benefits.