Senior Digital and Mixed-Signal Modeling/Verification Engineer

Apple Inc.; Cupertino (CA); On-site; USD 185,000 - 325,000; Full time

Job summary

Apple Inc. is seeking a Digital/Mixed Signal Modeling/Verification Engineer to verify the functionality and performance of Apple’s premier SoCs.

You will own RNM/SystemVerilog behavioral modeling of analog/RF blocks and set up AMS environments with analog designers, working in a fast-paced hardware team. The role focuses on developing self-checking models, creating assertions, and debugging complex testbenches to ensure compliance with analog and digital specs across the large SoC.

Qualifications

• BS in Electrical Engineering or related field with 10+ years of experience.
• Strong fundamentals in analog/RF circuit theory/topologies.
• Experience with Cadence mixed-signal verification environment.

Responsibilities

• Develop RNM RF/Analog models in SystemVerilog.
• Develop models with self-checking techniques.
• Assess required model accuracy level for verification goals.
• Develop assertions to ensure analog/digital specs are respected and provide digital verification criteria.
• Work with Analog designers setting up AMS simulation environment.
• Debug complex chip digital-on-top testbenches and identify root causes of failures.

Skills

Analog/RF theory

Self-checking techniques

Debug complex testbenches

AMS simulation

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Cadence mixed signal verification

SystemVerilog

AMS environment setup

Job description

Apple Inc. is seeking a Digital/Mixed Signal Modeling/Verification Engineer to verify the functionality and performance of Apple’s premier SoCs.

You will own RNM/SystemVerilog behavioral modeling of analog/RF blocks and set up AMS environments with analog designers, working in a fast-paced hardware team. The role focuses on developing self-checking models, creating assertions, and debugging complex testbenches to ensure compliance with analog and digital specs across the large SoC.