Senior Memory Subsystem Architect for DDR5/6 & HBM

Rambus; San Jose (CA); Hybrid; USD 180,000 - 334,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Rambus is seeking a Senior Principal Engineer to join the MIC team in San Jose, CA. You will lead architecture and development for next‑generation memory subsystems, including DDR5/DDR6, LPDDR4/5/6, and HBM derivatives, and drive PHY, SI, and system integration decisions.

The role partners with ASIC, firmware, validation, and platform engineering to deliver robust server and data-center memory solutions, reporting to the VP of Engineering in a hybrid work setting.

Qualifications

• Master’s degree in Electrical or Computer Engineering or related discipline required.
• 12+ years of industry experience in semiconductor, ASIC, memory, or high-speed interface development.
• Proven experience leading complex technical projects and influencing architectural decisions.
• Strong technical leadership across multidisciplinary teams including ASIC, PHY, firmware, validation, system architecture, and platform engineering.

Responsibilities

• Lead the architecture, design, and development of next-generation memory subsystem solutions.
• Drive technical decisions related to memory interfaces, PHY architecture, signal & power integrity, and system integration.
• Define subsystem requirements and translate system-level needs into architecture and design specifications.
• Provide technical leadership across multidisciplinary teams including ASIC, PHY, firmware, validation, system architecture, and platform engineering.
• Develop and maintain architecture specifications, design requirements, and technical documentation.
• Present proposals, design reviews, and architecture recommendations to leadership, customers, and ecosystem partners.

Skills

System Architecture Leadership

DDR5/DDR6/LPDDR5/HBM Memory Expertise

High-Speed PHY Design

Tx/Rx Circuit Architecture

DFE/CTLE Equalization Techniques

I2C

I3C

USB Interfaces

Digital Design & Verification

Technical Specification Development

Analytical Problem Solving

Executive-Level Presentations

Education

Master’s Degree in Electrical Engineering or Computer Engineering

Job description

Rambus is seeking a Senior Principal Engineer to join the MIC team in San Jose, CA. You will lead architecture and development for next‑generation memory subsystems, including DDR5/DDR6, LPDDR4/5/6, and HBM derivatives, and drive PHY, SI, and system integration decisions.

The role partners with ASIC, firmware, validation, and platform engineering to deliver robust server and data-center memory solutions, reporting to the VP of Engineering in a hybrid work setting.