Senior High-Speed Analog/Mixed-Signal Designer (DDR/IP)

Monolithic Power Systems Inc.; San Jose (CA); Sur place; USD 180 000 - 240 000; Plein temps

Résumé du poste

Monolithic Power Systems, Inc. in San Jose, CA is seeking a memory design engineer to define, specify, simulate and implement DDR/LPDDR IPs and related high-speed circuits. The role centers on analog and digital block design, architecture coordination, and pre-silicon verification.

You will own design, simulation, and characterization of high-speed blocks, collaborate with system teams, mentor junior engineers, and contribute to development flows while driving test plans and silicon bring-up.

Qualifications

• MS EE with 7+ years or PhD EE with 5+ years in analog/mixed-signal circuit design.
• Experience in high-speed analog circuits such as Transmitter, Receiver, PLL, DLL, PI or clock distribution.
• Solid knowledge of design tradeoffs and building blocks like bias, op-amp and LDO.
• Experience with memory interfaces (DDR4/5) or serial links (PCIe).
• Experience with Verilog-A, Verilog, and MATLAB modeling.
• Experience in leading R&D and future technology development projects.

Responsabilités

• Ownership of high speed analog/mixed signal designs at chip and block level
• Design, simulate and characterize high-performance and high-speed circuits
• Create high level model for design tradeoff analysis and behavior model for verification simulations
• Work with digital/system teams to define architecture and design plan to achieve budget, schedule and project deliverable goal
• Create floor plan and work with layout team to demonstrate post extraction performance
• Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow
• Work with the lab and system team for test plan, silicon bring-up and characterization
• Understand and disseminate applicable standards and its relevance in a given project to team
• Mentor junior designers
• Participate and contribute to the definition of development flows that improve efficiency and quality of design execution

Connaissances

Analog/mixed-signal design

High-speed circuit design

Memory interfaces (DDR4/5, PCIe)

Verilog-A / Verilog / MATLAB modeling

Leadership / mentoring

Architecture and design planning

Formation

MS EE

PhD EE

Description du poste

Monolithic Power Systems, Inc. in San Jose, CA is seeking a memory design engineer to define, specify, simulate and implement DDR/LPDDR IPs and related high-speed circuits. The role centers on analog and digital block design, architecture coordination, and pre-silicon verification.

You will own design, simulation, and characterization of high-speed blocks, collaborate with system teams, mentor junior engineers, and contribute to development flows while driving test plans and silicon bring-up.