Director of Validation Engineering - High-Speed Memory

Rambus.com; San Jose (CA); Presencial; USD 189 000 - 351 000; Tempo integral

Resumo da oferta

Rambus is seeking a Technical Director Validation Engineer to lead lab validation of high-speed memory interface products. The role focuses on automating data collection and building validation environments to ensure performance and specification compliance.

The candidate will work with DDR topologies, high-speed signaling, and lab equipment, mentoring teams and driving test methodologies across silicon design and applications teams.

Qualificações

• Experience in bench testing and characterization of high-speed memory IO devices.
• Proficiency with validation hardware and board design fundamentals.
• Skilled in high-speed lab equipment such as oscilloscopes, BERTs, and signal generators.
• Hands-on lab work and writing software for lab automation, especially Python.

Responsabilidades

• Lab bring-up and validation of high-speed memory buffer semiconductor products.
• Develop test methodologies for validating silicon designs against specifications.
• Develop scripts for automating lab equipment and for analyzing lab data.
• Lead validation tasks on bench planning, preparation, characterization execution, methodology improvements.
• Work with silicon design teams to develop experiments, drive data collection, and present results analysis.
• Provide inputs to FPGA, system, and PCB design requirements.
• Support Applications Team in understanding and resolving customer issues.

Conhecimentos

Bench testing

High-speed signaling

Lab automation

Team player

Memory IO knowledge

Formação académica

B.S./M.S. in Electrical Engineering

Ferramentas

Python

Oscilloscopes

BERTs

Signal generators

Logic analyzers

Descrição da oferta de emprego

Rambus is seeking a Technical Director Validation Engineer to lead lab validation of high-speed memory interface products. The role focuses on automating data collection and building validation environments to ensure performance and specification compliance.

The candidate will work with DDR topologies, high-speed signaling, and lab equipment, mentoring teams and driving test methodologies across silicon design and applications teams.