Senior High-Speed Analog/Mixed-Signal Designer (DDR/Memory)

MPS Hangzhou; San Jose (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Monolithic Power Systems, Inc. (MPS) is seeking a seasoned memory design engineer to support DDR/LPDDR IP development, with focus on analog/mixed-signal circuit design and high-speed data paths. Location: San Jose, CA.

You will define specifications, simulate, and implement future DDR/LPDDR IPs, collaborating with digital and system teams. The role emphasizes chip- and block-level design ownership, test planning, silicon bring-up, and mentorship of junior engineers within a leading semiconductor

Qualifications

• MS EE with 7+ years or PhD EE with 5+ years in analog/mixed-signal circuit design.
• Experience with high-speed analog circuits like Transmitter, Receiver, PLL, DLL, PI or clock distribution.
• Experience with memory interfaces such as DDR4/5 or PCIe is highly desirable.

Responsibilities

• Ownership of high speed analog/mixed signal designs at chip and block level.
• Design, simulate and characterize high-performance and high-speed circuits.
• Create high level model for design tradeoff analysis and behavior model for verification simulations.
• Work with digital/system teams to define architecture and design plan to achieve budget, schedule and project deliverable goal.
• Create floor plan and work with layout team to demonstrate post extraction performance.
• Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow.
• Work with the lab and system team for test plan, silicon bring-up and characterization.
• Understand and disseminate applicable standards and its relevance in a given project to team.
• Mentor junior designers
• Participate and contribute to development flows that improve efficiency and quality of design execution.

Skills

Analog/mixed-signal design

High-speed circuits

Verilog-A

Verilog

MATLAB

DDR/Memory interfaces

Education

MS EE

PhD EE

Tools

Verilog-A

Verilog

MATLAB

Job description

Monolithic Power Systems, Inc. (MPS) is seeking a seasoned memory design engineer to support DDR/LPDDR IP development, with focus on analog/mixed-signal circuit design and high-speed data paths. Location: San Jose, CA.

You will define specifications, simulate, and implement future DDR/LPDDR IPs, collaborating with digital and system teams. The role emphasizes chip- and block-level design ownership, test planning, silicon bring-up, and mentorship of junior engineers within a leading semiconductor