Senior Analog IC Design & Transceiver Architect

Synopsys, Inc.; Boxborough (MA); On-site; USD 180,000 - 260,000; Full time

Job summary

Synopsys, Inc. is seeking an exceptionally qualified IC Design Engineer with a PhD or MSc and extensive analog IC design experience in FinFET technologies.

The role focuses on memory, SerDes, and D2D sub-circuits, including high-speed receivers and DAC-based transmitters, with strong emphasis on clocking circuits and DSP-based equalization. The position involves leading novel transceiver architectures, ensuring design quality across layout and verification teams, and presenting results at

Qualifications

• PhD with 8+ years or MSc with 10+ years of analog IC design.
• Experience with FinFET technologies and transistor-level design.
• Expertise in Memory/SerDes/D2D sub-circuits including receivers and DAC/ADC.
• Proficiency with SPICE and scripting (TCL, Perl, Python, MATLAB).

Responsibilities

• Review UCIe and D2D standards to develop novel transceiver architectures.
• Develop circuit architectures addressing bottlenecks for power, area, and performance.
• Collaborate across geographies to streamline design and verification strategies.
• Oversee PHY level physical layout to minimize parasitics and process variation.
• Present and review simulation data to internal teams and external panels/customers.
• Document design features and test plans, support electrical characterization of D2D IP.

Skills

FinFET tech

Analog IC design

Transistor-level design

Memory/SerDes/D2D

Receive equalizers

DAC transmitters

DSP/clocking circuits

SPICE simulators

Scripting: TCL/Perl/C/Python

MATLAB

Education

PhD in Electrical Engineering

MSc in Electrical Engineering

Tools

Schematic entry tools

Physical layout tools

Design verification tools

Job description

Synopsys, Inc. is seeking an exceptionally qualified IC Design Engineer with a PhD or MSc and extensive analog IC design experience in FinFET technologies.

The role focuses on memory, SerDes, and D2D sub-circuits, including high-speed receivers and DAC-based transmitters, with strong emphasis on clocking circuits and DSP-based equalization. The position involves leading novel transceiver architectures, ensuring design quality across layout and verification teams, and presenting results at