Lead Analog Layout Engineer — High-Speed CMOS for AI Infra

Celero Communications, Inc.; Oregon; Híbrido; USD 120.000 - 170.000; Jornada completa

Descripción de la vacante

Celero Communications, Inc. is seeking a High-Speed Analog Layout Design Engineer to drive the layout development of analog and mixed-signal IP blocks for high-performance optical communication systems.

You will lead from floor planning to final verification, collaborating with circuit designers and CAD/PDK teams, and mentoring junior layout engineers across time zones. The role requires deep expertise in layout best practices, device matching, noise isolation, ESD protection, and parasitic

Formación

• Minimum 1+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
• Proven track record of top-level IP layout macros or full-chip layout at FinFET nodes (TSMC preferred).
• Experience with preparing IPs for handoff to Physical Design.
• Familiarity with LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules.

Responsabilidades

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through final verification.
• Collaborate with schematic designers to optimize layouts for performance, matching, symmetry, and reliability.
• Mentor junior layout engineers/contractors across multiple time zones; enforce best practices in layout and verification.
• Perform and debug LVS, DRC, PERC, ERC, and other signoff checks with industry tools.
• Contribute to chip-level planning including top-level floor planning, block integration, and power/ground grid design.
• Participate in layout design reviews and provide technical leadership for layout quality and schedule adherence.
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python).

Conocimientos

Analog layout

Mixed-signal layout

Floor planning

LVS/DRC

Cadence Virtuoso

Calibre

Pegasus

Python scripting

Mentoring

Team collaboration

Herramientas

SKILL

TCL

Python

Descripción del empleo

Celero Communications, Inc. is seeking a High-Speed Analog Layout Design Engineer to drive the layout development of analog and mixed-signal IP blocks for high-performance optical communication systems.

You will lead from floor planning to final verification, collaborating with circuit designers and CAD/PDK teams, and mentoring junior layout engineers across time zones. The role requires deep expertise in layout best practices, device matching, noise isolation, ESD protection, and parasitic