Senior PLL Design Engineer - High-Speed Transceivers

Celero Communications; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications is seeking a High-Speed CMOS PLL Analog Design Engineer to deliver transformative High-Speed Interconnect Technology. You will play a key role in designing PLLs for next generation optical transceivers and ADC/DAC systems.

The ideal candidate has a Master’s degree or PhD in Electrical Engineering and over 5 years of experience in PLL design, with extensive knowledge of advanced node technologies. This role offers a competitive salary based on skills and experience.

Qualifications

• 5+ years of relevant experience in PLL design and production-level tape-out experience.
• Extensive experience with advanced node technologies (16nm to 2nm processes).
• Proficient in Cadence Virtuoso and system-level modelling.

Responsibilities

• Architect and design PLLs for next generation transceivers.
• Supervise and verify layouts produced by layout engineers.
• Conduct performance characterization using advanced lab equipment.

Skills

PLL design

Analog/mixed-signal design

Cadence Virtuoso

Phase noise analysis

Electromagnetic simulation

Education

Master’s degree or PhD in Electrical Engineering

Tools

MATLAB

EMX/HFSS

Job description

Celero Communications is seeking a High-Speed CMOS PLL Analog Design Engineer to deliver transformative High-Speed Interconnect Technology. You will play a key role in designing PLLs for next generation optical transceivers and ADC/DAC systems.

The ideal candidate has a Master’s degree or PhD in Electrical Engineering and over 5 years of experience in PLL design, with extensive knowledge of advanced node technologies. This role offers a competitive salary based on skills and experience.