Principal Analog Design Engineer – High-Speed Interconnects

Celero Communications, Inc.; San Jose (CA); Presencial; USD 140 000 - 210 000; Tempo integral

Resumo da oferta

Celero Communications, Inc. is seeking an experienced Principal Analog Design Engineer in San Jose, CA.

You will architect and develop high-speed analog circuits for transceivers and related functions, lead layout supervision, and drive verification across CMOS processes. The role requires a Master’s or PhD in Electrical Engineering with 5+ years in analog design, strong fundamentals, and proficiency in Virtuoso/Spectre/ADE, as well as EM and high-frequency design knowledge.

Qualificações

• Master’s degree or PhD in Electrical Engineering or related field.
• 5+ years of experience in analog design.
• Strong fundamentals in analog circuit design for broadband amplification and clocking.
• Experience with design verification tools (Virtuoso, Spectre, ADE) is essential.
• Familiarity with CMOS design and verification flows and self-heating/electromigration considerations.
• Knowledge of EM tools (EMX, Momentum, HFSS) and high-frequency design concepts.

Responsabilidades

• Design high-speed analog circuits (broadband amplifiers, VGA, CTLE, DRV).
• Lead clock generation and distribution (VCOs, PLL, clock distribution).
• Develop fundamental analog blocks (bandgap refs, LDOs, temp sensors).
• Contribute to next-gen optical transceiver development.
• Oversee analog layout activities in advanced process nodes.

Conhecimentos

Analog design fundamentals

High-speed design

Clock generation

CMOS design

Communication

Documentation

FinFET layouts

RF/high-frequency design

Formação académica

Master’s degree in Electrical Engineering

PhD in Electrical Engineering

Ferramentas

Virtuoso

Spectre

ADE

EMX

Momentum

HFSS

Descrição da oferta de emprego

Celero Communications, Inc. is seeking an experienced Principal Analog Design Engineer in San Jose, CA.

You will architect and develop high-speed analog circuits for transceivers and related functions, lead layout supervision, and drive verification across CMOS processes. The role requires a Master’s or PhD in Electrical Engineering with 5+ years in analog design, strong fundamentals, and proficiency in Virtuoso/Spectre/ADE, as well as EM and high-frequency design knowledge.