Senior Advanced Packaging / Substrate Design Engineer (2.5D/3D Chiplets)

black.ai; Tempe (AZ); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Competitive salary

Early-stage equity opportunities

401(k) and other benefits

Health, dental, and vision coverage

Job summary

Syenta is seeking a Senior Advanced Packaging Design Engineer to lead physical layout and floor planning for 2.5D/3D interposers and high-density RDLs. You will drive die-to-package and package-to-board co-design, collaborating with ASIC, SI, and PI teams to ensure robust designs.

With 5+ years in semiconductor packaging, you will tackle design verification, DFM collaboration, and reliability optimization to push performance while managing manufacturability and thermal/structural challenges.

Qualifications

• BS/ MS in a technical discipline relevant to semiconductor packaging.
• 5+ years in semiconductor packaging layout, substrate design, or physical verification.

Responsibilities

• Physical Layout & Floor planning: lead the design, floor planning, pad/bump allocation, and complex routing of multi-layer organic substrates and 2.5D/3D interposer architectures.
• Co-Design Execution: drive die-to-package and package-to-board co-design with ASIC, SI, and PI teams.
• Design Verification: run and resolve DRC, LVS, and electrical rule checks for fine-pitch packaging tech.
• DFM & Manufacturing Collaboration: work with foundries/OSATs for DFM compliance and build-up sequences.
• Reliability Optimization: coordinate with thermal and mechanical teams to mitigate warpage, CTE mismatch, and thermo-mechanical stress.

Skills

Physical layout design

2.5D/3D IC integration

High-speed signal design

Power integrity

Cross-functional collaboration

Education

B.S. or M.S. in Electrical Engineering / Computer Engineering / Materials Science

Tools

Synopsys 3DIC Compiler

Cadence Allegro Package Designer Plus

Cadence Innovus

Siemens Xpedition Substrate Integrator

Calibre

Job description

About Syenta

Syenta is pioneering a new era in semiconductor manufacturing with our groundbreaking Localised Electrochemical Manufacturing (LEM) technology. Our manufacturing products build cutting edge advanced packaging for the semiconductor industry by combining patterning and metallization into a single tool. We do that by achieving high-speed, high-resolution metallization at significantly lower costs and energy use, while minimizing emissions and waste.

Founded in Australia, our growing footprint in the US represents a key milestone in our journey. We are building a world-class team where seasoned engineers and ambitious emerging talent collaborate to solve some of the toughest challenges in semiconductor manufacturing.

About the Role

We are seeking a Senior Advanced Packaging Design Engineer to drive the physical design, layout, and implementation of next-generation heterogeneous integration platforms. In this role, you will be at the forefront of semiconductor innovation, designing complex 2.5D and 3D organic substrate interposers, high-density RDLs, and chiplet architectures for high-performance computing (HPC) and AI applications.

If you have a passion for pushing the boundaries of physical layout, die-to-package co-design, and advanced substrate manufacturing, we want you on our team.

Responsibilities

• Physical Layout & Floor planning: Lead the physical design, floor planning, pad/bump allocation, and complex routing of multi-layer organic substrates and 2.5D/3D interposer architectures.
• Co-Design Execution: Drive die-to-package and package-to-board co-design, collaborating closely with ASIC design, signal integrity (SI), and power integrity (PI) engineering teams.
• Design Verification: Run and resolve advanced Design Rule Checks (DRC), Layout Versus Schematic (LVS), and electrical rule checks specific to fine-pitch packaging technologies.
• DFM & Manufacturing Collaboration: Work directly with substrate foundries and OSATs to ensure design-for-manufacturing (DFM) compliance, handling build-up sequences, microvia rules, and coreless substrate constraints.
• Reliability Optimization: Coordinate with thermal and mechanical engineering teams to mitigate warpage, CTE mismatch, and thermo-mechanical stress in organic substrate designs.

Requirements

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, or a related technical discipline.
• Experience: 5+ years of hands-on experience in semiconductor packaging layout, substrate design, or physical verification.
• Domain Knowledge: Deep understanding of 2.5D/3D IC integration, chiplet architectures, silicon bridges/interposers, and advanced organic substrate technologies (ABF build-up, fine-pitch routing).
• EDA Tool Proficiency (Must-Have): Proven mastery of industry-standard advanced packaging EDA tools, including:
• Synopsys: 3DIC Compiler, Icepak and/or Flotherm
• Cadence: Allegro Package Designer Plus / Innovus
• Siemens (Mentor): Xpedition Substrate Integrator / Calibre

• Analysis Awareness: Familiarity with power integrity, signal integrity, and thermal-mechanical modeling tools (e.g., Ansys Redhawk,HFSS).
• Deep expertise in high-speed signal design, including mitigation of crosstalk, reflections, and impedance mismatches
• Solid foundational knowledge across electrical, materials, thermal, and/or mechanical engineering disciplines
• Strong analytical and problem-solving skills, with the ability to operate effectively in a fast-paced, cross-functional environment

Why Choose Syenta?

We’re passionate about building a diverse, people-first company. We believe that our culture of collaboration and mutual respect fuels the kind of innovation that can redefine an industry.

What We Offer

• Competitive salary
• Early-stage equity opportunities
• Potential 401(k) and other benefits
• Comprehensive health, dental, and vision coverage plans, supported by Company
• Professional Growth – We’re scaling fast, so responsibilities can expand significantly in tandem with the business
• Team Events – Annual company event in Australia to collaborate and celebrate
• Work-Life Balance – Flexible leave policies and an understanding that meaningful work can coexist with a fulfilling personal life
• 15 days PTO and 10 days sick leave

Syenta is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, age, or any other characteristic protected by law.