Senior Packaging Architect – 3D/SiP (Hybrid)

Renesas; San Jose (CA); Hybrid; USD 200,000 - 240,000; Full time

Benefits offered by this job

Bonus opportunities

Job summary

Renesas Electronics America in San Jose is seeking a Principal Package Design Engineer to lead next-generation packaging for high-performance semiconductors, focusing on architecture, simulation, and cross-functional collaboration with design, product engineering, manufacturing, and suppliers.

You will drive advanced packaging initiatives (2.5D/3D, SiP, BGA/CSP) and define stack-ups, materials, and interconnect strategies, ensuring manufacturability and reliability through DOE, qualification,

Qualifications

• MSc or PhD in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field.
• 5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration.
• Strong hands-on knowledge of advanced packaging technologies, materials, assembly processes, and application system integration as they apply to AI infrastructure and data center power management.
• Deep understanding of thermal, mechanical, and electrical interactions in package design and extensive, hands-on model setup, simulations, and analysis. Strong background in CAD and simulation tools. Experience with package reliability testing and qualification standards.
• Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains.
• Proven ability to troubleshoot packaging failures, drive root cause/corrective action, and demonstrate strong project leadership and cross-functional communication skills.

Responsibilities

• Lead the design, development, and qualification of advanced semiconductor packaging solutions, including Flip-chip, 2.5D/3D packaging, SiP and BGA/CSP.
• Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements with deep simulation expertise.
• Drive OSAT selection and development for new product introductions (NPI).
• Collaborate with IC design, product definers, substrate, board, thermal, reliability, applications, and manufacturing teams for package compatibility and performance.
• Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
• Perform simulations and analysis on signal integrity, power integrity, thermal performance, mechanical stress, and DFM.

Skills

Leadership

Problem solving

Cross-functional collaboration

Communication

Education

MSc or PhD in Electrical Engineering or related field

Tools

Cadence Allegro Package Designer

SolidWorks

ANSYS

COMSOL

JMP / Minitab

CAD software

Job description

Renesas Electronics America in San Jose is seeking a Principal Package Design Engineer to lead next-generation packaging for high-performance semiconductors, focusing on architecture, simulation, and cross-functional collaboration with design, product engineering, manufacturing, and suppliers.

You will drive advanced packaging initiatives (2.5D/3D, SiP, BGA/CSP) and define stack-ups, materials, and interconnect strategies, ensuring manufacturability and reliability through DOE, qualification,