Senior RTL Design Engineer - Remote SoC Architect

Actalent; Santa Clara (CA); À distance; USD 200 000 - 500 000; Plein temps

Avantages offerts par ce poste

Medical, dental & vision

401(k) Retirement Plan

Life Insurance

Short/long-term disability

HSA

Paid time off

Résumé du poste

Actalent is seeking a Senior RTL Design Engineer to design, implement, and optimize RTL for portions of the Velaura SoC. You will collaborate with architects, software teams, and cross-disciplinary engineers to deliver robust microarchitectures.

You will work on hardware/software co-design, define hardware interfaces, and optimize for performance, power, area, and reliability, while partnering with verification and physical design teams throughout the cycle.

Qualifications

• Proven experience designing RTL for complex digital systems.
• Strong understanding of computer architecture and microarchitecture.
• Proficient with Verilog/SystemVerilog and modern RTL design methodologies.
• Familiar with performance, power, and area tradeoffs in SoC design.
• Experience with hardware/software co-design and system-level optimization.

Responsabilités

• Design, implement, and optimize RTL for key portions of the Velaura SoC.
• Collaborate with architects to develop robust and efficient microarchitectures.
• Participate in hardware/software co-design discussions across AI workloads, memory systems, and runtime software.
• Define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions with software teams.
• Contribute to compute engines, memory subsystems, interconnect fabrics, and other core SoC infrastructure.
• Optimize designs for performance, power, area, scalability, and reliability.
• Partner with verification and physical design teams throughout the development cycle.
• Analyze performance bottlenecks and propose architectural and implementation improvements.
• Leverage AI-assisted development workflows to improve productivity and design exploration.
• Participate in design reviews and foster a culture of technical excellence.

Connaissances

RTL design expertise

Verilog/SystemVerilog

microarchitecture understanding

hardware/software co-design

performance/power/area tradeoffs

debugging and problem solving

collaborative engineering

AI workflows familiarity

Description du poste

Actalent is seeking a Senior RTL Design Engineer to design, implement, and optimize RTL for portions of the Velaura SoC. You will collaborate with architects, software teams, and cross-disciplinary engineers to deliver robust microarchitectures.

You will work on hardware/software co-design, define hardware interfaces, and optimize for performance, power, area, and reliability, while partnering with verification and physical design teams throughout the cycle.