RTL Lead – Physical AI Compute

Velaura AI, Inc.; Santa Clara (CA); Hybrid; USD 200,000 - 300,000; Full time

Benefits offered by this job

Medical, dental, and vision coverage

Paid time off

Flexible work arrangements

Professional development opportunities

Equity compensation

Job summary

Velaura is seeking an experienced RTL Lead to drive the implementation of our next-generation Physical AI SoC. The role blends architectural influence with hands-on technical leadership, collaborating with system architects, AI architects, performance modelers, and software engineers to turn innovative concepts into production-quality silicon.

You will mentor engineers, shape design methodologies, and oversee RTL across compute engines, memory subsystems, interconnects, and system infrastructure

Qualifications

• Strong RTL design experience in complex SoCs, CPUs, GPUs, AI accelerators, networking devices, or related systems.
• Deep understanding of digital design fundamentals and microarchitecture.
• Experience with Verilog/SystemVerilog and modern RTL development methodologies.
• Familiarity with memory systems, interconnect fabrics, cache hierarchies, and system-level data movement.
• Experience balancing performance, power, area, and design complexity.
• Proven ability to drive complex technical projects from concept through silicon bring-up.
• Experience with hardware/software co-design and performance optimization across the full system stack.
• Familiarity with AI runtimes, operating systems, firmware, drivers, or other system software layers is highly desirable.

Responsibilities

• Lead RTL development across key portions of the Velaura SoC.
• Collaborate with architects to translate system requirements into robust microarchitectures.
• Drive hardware/software co-design across AI workloads, memory systems, runtime software, and system architecture.
• Partner closely with software teams to define programming models, execution flows, memory hierarchies, and performance-critical interfaces.
• Drive design decisions across compute engines, memory subsystems, interconnect, control logic, and system infrastructure.
• Develop high-quality, power-efficient, and scalable RTL implementations.
• Conduct architecture and RTL reviews to ensure performance, power, and area goals are achieved.
• Work closely with performance modeling, verification, physical design, and software teams throughout the development cycle.
• Help establish engineering processes and design methodologies as the organization grows.
• Mentor and develop other RTL engineers.

Skills

RTL design experience

SoC architectures

Verilog/SystemVerilog

microarchitecture

hardware/software co-design

performance optimization

system-level tradeoffs

mentoring engineers

digital design fundamentals

memory systems/interconnect

Job description

Role Overview

We are seeking an experienced RTL Lead to help drive the implementation of Velaura’snext-generation Physical AI SoC. This role combines architectural influence withhands-on technical leadership. You will work closely with system architects, AIarchitects, performance modelers, and software engineers to transform innovativearchitectural concepts into production-quality silicon. The ideal candidate is equallycomfortable discussing system-level tradeoffs and reviewing critical RTLmicroarchitecture. You should enjoy solving challenging technical problems, mentoring
engineers, and helping build a high-performance engineering culture.

Responsibilities

• Lead RTL development across key portions of the Velaura SoC.
• Collaborate with architects to translate system requirements into robustmicroarchitectures.
• Drive hardware/software co-design across AI workloads, memory systems,runtime software, and system architecture.
• Partner closely with software teams to define programming models, executionflows, memory hierarchies, and performance-critical interfaces.
• Drive design decisions across compute engines, memory subsystems,interconnect, control logic, and system infrastructure.
• Develop high-quality, power-efficient, and scalable RTL implementations.
• Conduct architecture and RTL reviews to ensure performance, power, and areagoals are achieved.
• Work closely with performance modeling, verification, physical design, andsoftware teams throughout the development cycle.
• Help establish engineering processes and design methodologies as theorganization grows.
• Mentor and develop other RTL engineers.

Required Qualifications

• Strong RTL design experience in complex SoCs, CPUs, GPUs, AI accelerators, networking devices, or related systems.
• Deep understanding of digital design fundamentals and microarchitecture.
• Experience with Verilog/SystemVerilog and modern RTL developmentmethodologies.
• Familiarity with memory systems, interconnect fabrics, cache hierarchies, and system-level data movement.
• Experience balancing performance, power, area, and design complexity.
• Proven ability to drive complex technical projects from concept through silicon bring-up.
• Experience with hardware/software co-design and performance optimization across the full system stack.
• Familiarity with AI runtimes, operating systems, firmware, drivers, or othersystem software layers is highly desirable.

Preferred Qualifications

• Experience with AI accelerators, machine learning hardware, or edge AI platforms.
• Experience with robotics, autonomous systems, automotive, aerospace, or other real-time computing environments.
• Knowledge of low-power design techniques and power managementarchitectures.

$200,000 - $300,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company’s long-term success.

The base pay listed represents a good faith estimate that the Company reasonably expects to pay for this position at the time of hire. Actual compensation will depend on multiple factors, including the candidate's skills, qualifications, relevant experience, and geographic location.

In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well‑being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and PhysicalAI. Our solutions will enable robots, autonomous systems, drones, and other intelligentmachines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape thefuture of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity.

Qualified applicants will receive consideration for employment without regard to race,color, religion, national origin, gender, sexual orientation, gender identity, disability orprotected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mentaldisabilities. Applicants who would like to contact us regarding the accessibility of ourwebsite or who need special assistance or a reasonable accommodation for any part ofthe application or hiring process may contact us at: [e-mail]. This contact
information is for accommodation requests only. Evaluation of requests for reasonableaccommodation will be determined on a case-by-case basis.