Senior CPU CDC/RDC Engineer – SystemVerilog & RTL

Apple Inc.; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. in Santa Clara is seeking a senior hardware verification engineer to own the CDC/RDC sign-offs for CPU designs, collaborate with RTL and DV teams, and drive robust STA checks across multi-clock domains.

The role requires deep Verilog/SystemVerilog expertise, experience with CDC/RDC, EDA tools such as Synopsys or Real Intent, TCL/Perl scripting, and a track record of delivering safe, scalable designs in complex SoC environments.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Experience with Clock-Domain Crossing (CDC) and Reset Domain Crossing (RDC).
• Experience with at least one of the following: Synopsys or Real Intent tool.
• Scripting experience in TCL or Perl.
• Experience in Verilog.

Responsibilities

• Develop, improve, and maintain CDC and RDC sign-offs for CPU designs.
• Collaborate with RTL and DV teams to specify SystemVerilog assertions for CDC/RDC/STA constraints.

Skills

CDC

RDC

Verilog

SystemVerilog

SVA (SystemVerilog Assertions)

TCL

Perl

EDA tools (Synopsys/Real Intent)

Spyglass/PrimeTime/Meridian

Education

BS in Electrical Engineering or related field

Tools

Synopsys tools

Real Intent tools

Spyglass

PrimeTime

Meridian

Job description

Apple Inc. in Santa Clara is seeking a senior hardware verification engineer to own the CDC/RDC sign-offs for CPU designs, collaborate with RTL and DV teams, and drive robust STA checks across multi-clock domains.

The role requires deep Verilog/SystemVerilog expertise, experience with CDC/RDC, EDA tools such as Synopsys or Real Intent, TCL/Perl scripting, and a track record of delivering safe, scalable designs in complex SoC environments.