RTL Design Engineer

7Rays Semiconductors; San Jose (CA); On-site; USD 140,000 - 180,000; Full time

Job summary

7Rays Semiconductors is seeking an experienced CDC/RDC Engineer to verify and sign off on clock-domain and reset-domain crossings in advanced SoC designs. You will collaborate with RTL, Design, Physical Design, and Verification teams to resolve issues and ensure robust synchronization.

The role requires strong Verilog/SystemVerilog skills, and hands-on experience with CDC/RDC tools such as SpyGlass, Questa, and Cadence.

Qualifications

• 5+ years of experience in CDC/RDC verification and signoff.
• Strong knowledge of clock-domain crossing, metastability, and synchronization.
• Proficient in Verilog/SystemVerilog.
• Experience with CDC/RDC tools (SpyGlass/Questa/Cadence).

Responsibilities

• Perform CDC and RDC analysis, verification, and signoff for complex SoC designs.
• Develop and review CDC/RDC constraints, waivers, and methodologies.
• Analyze and debug clock-domain and reset-domain crossing violations.
• Work closely with RTL, Design, Physical Design, and Verification teams to resolve issues.
• Review RTL for proper clock/reset synchronization and identify potential metastability risks.
• Run CDC/RDC checks and generate detailed reports for design reviews and signoff.
• Support methodology development, automation, and scripting using Tcl/Python where required.
• Participate in design reviews and ensure CDC/RDC quality across multiple IPs and SoC blocks.

Skills

CDC verification

Clock-domain crossing

Reset-domain crossing

Metastability

Synchronizers

Verilog/SystemVerilog

ASIC/SoC design

Debugging

Tcl/Python scripting

CDC/RDC tools

Tools

Synopsys SpyGlass CDC/RDC

VC SpyGlass

Questa CDC

Cadence tools

Job description

We are looking for an experienced CDC/RDC Engineer to work on advanced SoC designs, focusing on Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) verification and signoff.

Responsibilities:

• Perform CDC and RDC analysis, verification, and signoff for complex SoC designs.
• Develop and review CDC/RDC constraints, waivers, and methodologies.
• Analyze and debug clock-domain and reset-domain crossing violations.
• Work closely with RTL, Design, Physical Design, and Verification teams to resolve issues.
• Review RTL for proper clock/reset synchronization and identify potential metastability risks.
• Run CDC/RDC checks and generate detailed reports for design reviews and signoff.
• Support methodology development, automation, and scripting using Tcl/Python where required.
• Participate in design reviews and ensure CDC/RDC quality across multiple IPs and SoC blocks.

Required Skills:

• Strong experience in CDC and RDC verification/signoff.
• Good understanding of clock-domain crossing, reset-domain crossing, metastability, synchronizers, and clock/reset architectures.
• Strong RTL knowledge with Verilog/SystemVerilog.
• Experience with CDC/RDC tools such as Synopsys SpyGlass CDC/RDC, VC SpyGlass, Questa CDC, or Cadence tools.
• Experience working on ASIC/SoC designs and advanced technology nodes.
• Good debugging and problem-solving skills.