Senior Full-Chip Physical Verification Engineer

Anysilicon; San Jose, Northern (CA, KY); Hybrid; USD 170,000 - 260,000; Full time

Job summary

Broadcom is seeking a senior ASIC verification engineer to join its sign-off flows team in San Jose. You will focus on physical verification, ESD checking, and package RDL routing, driving LVS/DRC/ANT/ERC checks and rule-deck debugging.

The role requires extensive full-chip verification experience and strong scripting skills with Perl, Tcl, or C shell to automate flows and debug issues across Cadence and Synopsys tools.

Qualifications

• Bachelor's degree with 12+ years of related experience or Master's degree with 10+ years of related experience.
• Extensive experience in full-chip physical verification and debugging.

Responsibilities

• Involved in sign-off flows including physical verification, ESD checking, and package RDL routing.
• Conduct full-chip physical verification (LVS/DRC/ANT/ERC).
• Understand and debug rule decks effectively.
• Engage in full-chip implementation as needed.

Skills

full-chip physical verification

block-level place & route

debug rule decks

Education

Bachelor's degree

Master's degree

Tools

Perl

Tcl

Csh

Calibre

Redhawk & Totem

Cadence Virtuoso

Cadence Innovus

Synopsys ICC2

Job description

Broadcom is seeking a senior ASIC verification engineer to join its sign-off flows team in San Jose. You will focus on physical verification, ESD checking, and package RDL routing, driving LVS/DRC/ANT/ERC checks and rule-deck debugging.

The role requires extensive full-chip verification experience and strong scripting skills with Perl, Tcl, or C shell to automate flows and debug issues across Cadence and Synopsys tools.