RTL Engineer for Physical AI Accelerators

Altera; San Jose (CA); On-site; USD 149,000 - 238,000; Full time

Job summary

Altera is seeking RTL Engineers to help develop hardware architectures for Physical AI workloads on FPGA and heterogeneous compute platforms. You will translate specs into synthesizable Verilog/SystemVerilog RTL and optimize designs for performance, area, power, and scalability.

Collaborate with verification teams to define strategies and support hardware bring-up. Qualifications include a Bachelor's degree in a related field and 3+ years in RTL design plus strong Verilog/SystemVerilog skills.

Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years of RTL design and digital logic development.
• Strong expertise in Verilog and/or SystemVerilog.
• Solid understanding of computer architecture, digital design fundamentals, and ASIC/FPGA design methodologies.
• Experience with simulation, debugging, and verification tools.
• Experience developing high-performance datapath, control logic, or accelerator architectures.
• Familiarity with synthesis, static timing analysis, and FPGA implementation flows.
• Strong analytical, debugging, and problem-solving skills.
• Excellent communication and collaboration abilities.

Responsibilities

• Design and develop RTL for FPGA and programmable hardware solutions supporting Physical AI applications.
• Translate architectural specifications into high-quality, synthesizable Verilog/SystemVerilog RTL.
• Create microarchitecture specifications and participate in architecture reviews.
• Optimize designs for performance, area, power, and scalability.
• Collaborate closely with design verification teams to define verification strategies and close functional coverage.
• Support FPGA implementation activities including synthesis, timing closure, and performance analysis.
• Work with firmware and software teams to enable hardware-software integration and system bring-up.
• Debug RTL, simulation, emulation, and silicon-related issues throughout the product lifecycle.
• Contribute to feature definition and architectural innovation for next-generation AI acceleration technologies.
• Participate in design reviews and maintain high standards for code quality and engineering excellence.

Skills

RTL design

Verilog

SystemVerilog

Digital logic

ASIC/FPGA design

Debugging tools

Synthesis

Timing analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related

Tools

Synopsys

Siemens EDA

Cadence

Job description

Altera is seeking RTL Engineers to help develop hardware architectures for Physical AI workloads on FPGA and heterogeneous compute platforms. You will translate specs into synthesizable Verilog/SystemVerilog RTL and optimize designs for performance, area, power, and scalability.

Collaborate with verification teams to define strategies and support hardware bring-up. Qualifications include a Bachelor's degree in a related field and 3+ years in RTL design plus strong Verilog/SystemVerilog skills.