NoC RTL Design Engineer for AI Accelerators

OpenAI, Inc.; San Francisco (CA); On-site; USD 287,000 - 485,000; Full time

Job summary

OpenAI is seeking an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. You will work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient hardware designs.

You will collaborate with silicon architects, hardware and software engineers, verification, and physical design teams to co‑design hardware solutions optimized for demanding AI workloads, with opportunities to influence

Qualifications

• Have strong hands-on experience with ASIC RTL design and microarchitecture development using SystemVerilog or Verilog.
• Have experience designing and implementing complex digital hardware blocks, from architecture and specification through RTL development and verification.
• Understand hardware architecture and microarchitecture tradeoffs, including performance, power, area, latency, and throughput.
• Have experience collaborating across architecture, software, verification, and physical design teams to develop optimized hardware solutions.
• Can reason about complex hardware systems, identify performance bottlenecks, and translate architectural requirements into efficient RTL implementations.
• Have experience with synthesis, timing closure, and physical implementation considerations.
• Enjoy working on ambiguous, technically challenging problems and taking ownership of designs from concept through integration.
• Bring experience with Network‑on‑Chip (NoC), networking, interconnect fabrics, packet‑based architectures, or high‑bandwidth data movement systems.
• Experience with AI accelerators, high‑performance computing, or hardware/software co‑design is a plus.

Responsibilities

• Design and implement high‑performance RTL for next‑generation AI accelerator silicon, from microarchitecture definition through implementation and integration.
• Collaborate with architecture and software teams to translate system‑level requirements into efficient hardware microarchitectures.
• Drive hardware/software co‑design efforts to optimize performance, power, area, and scalability for AI workloads.
• Develop and optimize RTL for complex datapaths, control logic, interconnects, and other critical silicon subsystems.
• Evaluate architectural and microarchitectural tradeoffs across bandwidth, latency, throughput, and resource utilization.
• Partner with design verification and formal verification teams to ensure functional correctness, develop verification strategies, and debug complex design issues.
• Work closely with physical design teams to optimize RTL for synthesis, timing closure, power, and area.
• Contribute to architecture reviews, design specifications, and cross‑functional discussions to influence future silicon designs.
• Support block‑level and SoC‑level integration, debugging, and performance optimization.

Skills

SystemVerilog

Verilog

ASIC RTL design

RTL development

NoC / interconnect

AI accelerators

Job description

OpenAI is seeking an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. You will work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient hardware designs.

You will collaborate with silicon architects, hardware and software engineers, verification, and physical design teams to co‑design hardware solutions optimized for demanding AI workloads, with opportunities to influence