Senior FPGA IP Software Engineer - RTL & System Bring-up

191 Altera Corporation; San Jose (CA); On-site; USD 133,000 - 213,000; Full time

Job summary

Altera is seeking an FPGA IP Software Development Engineer to design, integrate, validate, and debug FPGA-based systems for embedded and data-center applications. You will work on RTL development and system integration focusing on PCIe, EMIF, Ethernet IPs and HPS-based platforms.

You will collaborate with hardware and software teams to optimize performance, bring-up, and debugging of advanced SmartNIC and embedded solutions, leveraging C/C++, Python, and FPGA toolchains.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years of FPGA design and development experience.
• Strong RTL development experience with Verilog and SystemVerilog.
• Experience integrating FPGA IPs such as PCIe, Ethernet, EMIF, and ARM HPS.
• FPGA system bring-up, validation, and debugging.
• Knowledge of FPGA toolchains and implementation flows.

Responsibilities

• Design, develop, integrate, and validate RTL for FPGA-based systems.
• Collaborate with software teams on HW/SW co-design and integration.
• Develop drivers and software abstractions for FPGA acceleration.
• Support board bring-up and system-level validation.
• Drive process improvements and stay current with FPGA technologies.

Skills

Verilog

SystemVerilog

C/C++

Python

Education

Bachelor's Degree in Electrical Engineering or related field

Master's degree (preferred)

Tools

PCIe IPs

Ethernet IPs

EMIF

ARM HPS

Job description

Altera is seeking an FPGA IP Software Development Engineer to design, integrate, validate, and debug FPGA-based systems for embedded and data-center applications. You will work on RTL development and system integration focusing on PCIe, EMIF, Ethernet IPs and HPS-based platforms.

You will collaborate with hardware and software teams to optimize performance, bring-up, and debugging of advanced SmartNIC and embedded solutions, leveraging C/C++, Python, and FPGA toolchains.