FPGA RTL Engineer for Edge AI Accelerators

Altera Corporation; San Jose (CA); On-site; USD 149,000 - 238,000; Full time

Job summary

Altera Corporation in San Jose, California, seeks an RTL Engineer to design and verify high-performance digital logic powering Physical AI workloads on FPGA platforms. Translate architectures into synthesizable Verilog/SystemVerilog and work with architects, verification, firmware and software teams for scalable hardware solutions.

Strong background in computer architecture and RTL design is required, along with experience in simulation, debugging, and performance analysis.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 3+ years of RTL design and digital logic development.
• Strong Verilog/SystemVerilog experience and computer architecture fundamentals.
• Experience with simulation, debugging, and verification tools.
• Familiarity with FPGA implementation flows and performance analysis.

Responsibilities

• Design RTL for FPGA and programmable hardware solving Physical AI workloads.
• Translate architectures into synthesizable Verilog/SystemVerilog RTL.
• Create microarchitecture specifications and participate in architecture reviews.
• Optimize designs for performance, area, power, and scalability.
• Collaborate with verification, firmware, and software teams to enable HW-SW integration.

Skills

Verilog

SystemVerilog

Computer architecture

Digital design

ASIC/FPGA design

Simulation & debugging

Verification tools

Education

Bachelor's degree in Electrical/Computer Engineering or related

Masters/PhD preferred

Tools

Synopsys

Cadence

Siemens EDA

Job description

Altera Corporation in San Jose, California, seeks an RTL Engineer to design and verify high-performance digital logic powering Physical AI workloads on FPGA platforms. Translate architectures into synthesizable Verilog/SystemVerilog and work with architects, verification, firmware and software teams for scalable hardware solutions.

Strong background in computer architecture and RTL design is required, along with experience in simulation, debugging, and performance analysis.