Senior Physical Design Engineer: FPGA & SoC Innovation

Altera; San Jose (CA); On-site; USD 133,000 - 193,000; Full time

Job summary

Altera is seeking a highly motivated Senior Physical Design Engineer to join our Physical Design organization. You will implement custom IP and SoC designs from RTL through GDSII, driving physical implementation, timing closure, power optimization, and design signoff for next‑generation FPGA products.

You will collaborate with RTL designers, Design Verification, DFT, Timing, and CAD teams to deliver high‑quality silicon and contribute to continuous improvement of design methodologies and

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• 6+ years of hands-on experience with digital ASIC or SoC physical design implementation.
• 6+ years of experience performing RTL-to-GDSII physical design flows.
• 6+ years of experience with synthesis, floorplanning, place and route, and clock tree synthesis (CTS).
• 6+ years of experience performing static timing analysis (STA) and timing closure.
• 4+ years of experience with physical verification, including DRC, LVS, ERC, and signoff methodologies.
• 4+ years of experience using industry-standard physical design EDA tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, or equivalent.
• 3+ years of experience optimizing designs for power, performance, and area (PPA).
• 2+ years of experience supporting designs with multiple voltage or power domains.

Responsibilities

• Perform physical design implementation of custom IP and SoC designs from RTL through GDSII to create a manufacturing-ready design database.
• Execute all aspects of the physical design flow, including synthesis, floorplanning, place and route, clock tree synthesis (CTS), static timing analysis (STA), power and clock distribution, reliability analysis, and power/noise analysis.
• Perform physical verification and design signoff, including formal equivalence checking, static timing verification, reliability verification, power integrity analysis, layout verification, electrical rule checking (ERC), and structural design checking.
• Analyze implementation and signoff results, identify violations, and develop solutions that improve current and future product architectures.
• Apply expertise in physical clock design, timing closure, placement, routing, synthesis, DFT implementation, multiple power domain analysis, and coverage analysis using industry-standard EDA tools.
• Optimize physical designs to improve power, performance, frequency, and area (PPA).
• Collaborate with cross-functional engineering teams to resolve implementation challenges throughout the design cycle.
• Participate in the development and continuous improvement of physical design methodologies, design flows, and automation.

Skills

Analytical thinking

Collaboration

Communication

Multitasking

Education

Bachelor's degree in Electrical Engineering/Computer Engineering/CS

Master's degree (preferred)

Tools

Synopsys Fusion Compiler

ICC2

PrimeTime

Cadence Innovus

Job description

Altera is seeking a highly motivated Senior Physical Design Engineer to join our Physical Design organization. You will implement custom IP and SoC designs from RTL through GDSII, driving physical implementation, timing closure, power optimization, and design signoff for next‑generation FPGA products.

You will collaborate with RTL designers, Design Verification, DFT, Timing, and CAD teams to deliver high‑quality silicon and contribute to continuous improvement of design methodologies and