RTL Design Engineer – Mixed-Signal ASICs & Silicon Bring-Up

Teradyne; Reading (MA); On-site; USD 123,100 - 196,900; Full time

Benefits offered by this job

Comprehensive health benefits

Flexible Spending Accounts

Retirement savings plans

Paid vacation & holidays

Job summary

A leading tech company in North Reading, MA is seeking an experienced RTL Designer to develop specifications and RTL design for next-generation ASICs. This role involves collaboration with an Analog team and product architects, ensuring high-quality RTL and silicon success. Candidates must have a BSEE/MSEE and over 5 years of experience in logic design, including RTL in Verilog. The position offers a competitive salary, discretionary bonuses, and comprehensive benefits including health and retirement plans.

Qualifications

• 5+ years of experience in RTL design and logic design.
• Experience with high-speed memory and serial interfaces.
• Established understanding of DFT, state machines, and FIFOs.

Responsibilities

• Develop specifications, micro‑architecture, and RTL design of blocks.
• Collaborate with verification team for test plans and debug support.
• Provide timing constraints and support to Physical Design team.

Skills

RTL design in Verilog

Logic design

Scripting (Python, Tcl, Make)

Static timing analysis (STA)

High-speed data paths

Education

BSEE or MSEE in Electrical Engineering

Job description

A leading tech company in North Reading, MA is seeking an experienced RTL Designer to develop specifications and RTL design for next-generation ASICs. This role involves collaboration with an Analog team and product architects, ensuring high-quality RTL and silicon success. Candidates must have a BSEE/MSEE and over 5 years of experience in logic design, including RTL in Verilog. The position offers a competitive salary, discretionary bonuses, and comprehensive benefits including health and retirement plans.