RTL Design Engineer - DSP & Mixed-Signal

Apple Inc.; Cupertino (CA); On-site; USD 129,300 - 225,300; Full time

Benefits offered by this job

Medical & dental coverage

Retirement benefits

Stock programs

Relocation assistance

Tuition reimbursement

Job summary

Apple is seeking an RTL Design Engineer in Cupertino, California to advance mixed-signal and digital blocks in silicon. You will specify, design, verify, and support lab bring‑up for high‑speed RTL circuits with signal processing capabilities.

The role emphasizes Verilog/SystemVerilog RTL coding, design verification with assertions, and collaboration with analog, DSP, and verification teams to deliver silicon that meets performance goals.

Qualifications

• Bachelor's degree in Electrical Engineering.

Responsibilities

• RTL Design & Implementation: Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal processing pipelines
• DSP Algorithm Translation: Translate DSP concepts into efficient RTL implementations
• Design Verification: Write assertions and testbenches and participate in functional verification
• Integration & Bring-up: Collaborate with cross-functional teams to integrate IPs and support lab characterization
• Collaborative Problem-Solving: Work with analog designers, algorithm engineers, verification specialists, and system architects

Skills

RTL Design & Implementation

DSP Algorithm Translation

Design Verification

Integration & Bring-up

Collaborative Problem-Solving

GenAI in hardware design

Perl

Python

Education

Bachelors of Science in Electrical Engineering

Tools

Verilog simulators

linters

clock-domain crossing checkers

Synthesis

static timing analysis

design-for-test (DFT)

SystemVerilog assertions

Job description

Apple is seeking an RTL Design Engineer in Cupertino, California to advance mixed-signal and digital blocks in silicon. You will specify, design, verify, and support lab bring‑up for high‑speed RTL circuits with signal processing capabilities.

The role emphasizes Verilog/SystemVerilog RTL coding, design verification with assertions, and collaboration with analog, DSP, and verification teams to deliver silicon that meets performance goals.