RTL Design Engineer

Teradyne; Reading (MA); On-site; USD 123,100 - 196,900; Full time

Benefits offered by this job

Comprehensive health benefits

Flexible Spending Accounts

Retirement savings plans

Paid vacation & holidays

Job summary

A leading tech company in North Reading, MA is seeking an experienced RTL Designer to develop specifications and RTL design for next-generation ASICs. This role involves collaboration with an Analog team and product architects, ensuring high-quality RTL and silicon success. Candidates must have a BSEE/MSEE and over 5 years of experience in logic design, including RTL in Verilog. The position offers a competitive salary, discretionary bonuses, and comprehensive benefits including health and retirement plans.

Qualifications

• 5+ years of experience in RTL design and logic design.
• Experience with high-speed memory and serial interfaces.
• Established understanding of DFT, state machines, and FIFOs.

Responsibilities

• Develop specifications, micro‑architecture, and RTL design of blocks.
• Collaborate with verification team for test plans and debug support.
• Provide timing constraints and support to Physical Design team.

Skills

RTL design in Verilog

Logic design

Scripting (Python, Tcl, Make)

Static timing analysis (STA)

High-speed data paths

Education

BSEE or MSEE in Electrical Engineering

Job description

Location: North Reading, MA, US

Opportunity Overview

Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next‑generation products such as SOC and Memory Test Instruments. Teradyne’s products must be ahead of the semiconductor industry to enable customers to ship production chips/products. You will join a best‑in‑class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne’s next‑generation large Mixed‑Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bring‑up, and will have cutting‑edge AI tools available to optimize your productivity.

Responsibilities

• Develop specifications, micro‑architecture, and RTL design of mission‑critical blocks in collaboration with the chip architect.
• Integrate industry‑standard and Teradyne custom IPs.
• Collaborate with the verification team on test plans, debug support, and coverage closure to ensure high‑quality RTL and first‑pass silicon success.
• Provide timing constraints and STA support to the Physical Design team through timing closure.
• Offer post‑silicon lab bring‑up and debug support.

Qualifications

• BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
• Extensive logic design experience writing RTL in Verilog.
• Experience designing state machines, FIFOs, high‑speed data paths, arbitration logic, and DFT.
• Experience with logic synthesis and timing constraints.
• Experience with clock domain crossings (CDC) and static timing analysis (STA).
• Experience with high‑speed memory and serial interfaces.
• Experience with automation through scripting such as Python, Tcl & Make.

Compensation

The base salary range for this role is $123,100 - $196,900. This range is a good‑faith estimate, and the amount of base salary will correspond with experience and skill set. The range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of comprehensive health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

We are an equal‑opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment.