ASIC AI Accelerator Power Engineer

Google Inc.; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google Sunnyvale, CA, USA is seeking a Mid-level ASIC Power Engineer focused on ML accelerators. You will shape TPU power architecture, build power models, and drive power efficiency for data-center AI hardware, working on chip-wide power management and integration with AI/ML systems.

The role requires 8 years in silicon design or architecture, a Bachelor's in EE/CE/CS, and experience with power design and DVFS concepts.

Qualifications

• Bachelors degree in Electrical Engineering or related field.
• 8 years of experience in silicon design or architecture.
• Experience with power design, power modeling, and power reduction techniques.

Responsibilities

• Contribute to design power modeling and drive convergence to power goals.
• Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.

Skills

Power design

Power modeling

Power architecture

Power reduction

Mentoring

Problem solving

Open-ended problems

Education

Bachelors in EE/CE

Job description

Google Sunnyvale, CA, USA is seeking a Mid-level ASIC Power Engineer focused on ML accelerators. You will shape TPU power architecture, build power models, and drive power efficiency for data-center AI hardware, working on chip-wide power management and integration with AI/ML systems.

The role requires 8 years in silicon design or architecture, a Bachelor's in EE/CE/CS, and experience with power design and DVFS concepts.