RTL Design Engineer - ASIC IPs, Synthesis & Debug

I2Intech LLC; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

I2Intech LLC in San Jose, CA is seeking an ASIC RTL Design Engineer to develop clean, efficient RTL for IP blocks and subsystems, from micro-architecture specs to synthesis.

You will write and optimise Verilog/SystemVerilog, perform linting and timing analysis, and support verification teams with design walkthroughs, debug, and design reviews. This on-site role offers exposure to production silicon and growth opportunities.

Qualifications

• Degree-qualified candidate with hands-on RTL development experience.
• Strong understanding of FSMs, pipelining, arbitration, FIFOs and asynchronous interfaces.
• Experience with simulation, linting and timing analysis tools.

Responsibilities

• Write and optimise RTL for datapath and control logic.
• Create block-level micro-architecture documents and interface specifications.
• Run lint, CDC and RDC checks and resolve violations.
• Perform preliminary synthesis to evaluate timing and area.
• Support verification engineers with design walkthroughs and debugging.
• Participate in design reviews and maintain design documentation.

Skills

RTL design

FSMs and pipelining

Arbitration and FIFOs

Asynchronous interfaces

Python scripting

Verilog/SystemVerilog

Simulation and lint tools

Synthesis and static timing

Education

Bachelor's in Electrical/Computer Engineering

Master's preferred

Tools

Verilog

SystemVerilog

Lint tools

Synthesis tools

Job description

I2Intech LLC in San Jose, CA is seeking an ASIC RTL Design Engineer to develop clean, efficient RTL for IP blocks and subsystems, from micro-architecture specs to synthesis.

You will write and optimise Verilog/SystemVerilog, perform linting and timing analysis, and support verification teams with design walkthroughs, debug, and design reviews. This on-site role offers exposure to production silicon and growth opportunities.