Principal ASIC Design Engineer - RTL & Silicon Bringup

SiMa.ai, Inc.; San Jose (CA); On-site; USD 204,000 - 316,000; Full time

Benefits offered by this job

Private company equity

On-site in San Jose

Comprehensive benefits

Job summary

SiMa.ai, Inc. in San Jose, CA is seeking a Principal ASIC Design Engineer to own complex RTL blocks from concept through silicon bring-up.

The role emphasizes hands-on Verilog/SystemVerilog, block-level optimization, and collaboration with verification, physical design, and firmware teams in a fast-paced startup environment. You will drive ground-up design, timing closure, and DFT readiness while focusing on power, performance, and area targets.

Qualifications

• Requires a Master’s degree in Electrical/Computer Engineering or related field.
• 10+ years of ASIC design experience with block-level RTL and silicon development.
• Expert RTL design skills (Verilog/SystemVerilog), with synthesis, timing closure and DFT.
• Strong microarchitecture trade-off skills and block-level optimization for power, performance, and area.

Responsibilities

• Own microarchitecture definition and RTL implementation of complex blocks from concept through silicon.
• Drive ground-up block design from specification to RTL, integration, and bring-up.
• Develop synthesizable RTL with custom logic, protocol adaptation, and data-path optimizations.
• Define block interfaces and architectural trade-offs; ensure blocks meet timing, power, and area targets.
• Collaborate with verification, physical design, architecture, and firmware teams to validate blocks.
• Drive block-level synthesis, timing closure, and DFT readiness.

Skills

RTL design

Verilog/SystemVerilog

DFT concepts

Timing closure

Power, performance, area optimization

Post-silicon validation

Education

Master's degree in Electrical/Computer Engineering or related field

Tools

PCIe

UCIe

Lab equipment (oscilloscopes, logic analyzers)

Job description

SiMa.ai, Inc. in San Jose, CA is seeking a Principal ASIC Design Engineer to own complex RTL blocks from concept through silicon bring-up.

The role emphasizes hands-on Verilog/SystemVerilog, block-level optimization, and collaboration with verification, physical design, and firmware teams in a fast-paced startup environment. You will drive ground-up design, timing closure, and DFT readiness while focusing on power, performance, and area targets.