RTL Engineer

Canvendor; Dallas (TX); On-site; USD 110,000 - 170,000; Full time

Job summary

Canvendor in Dallas, TX seeks an RTL/ASIC Design Engineer with expert-level RTL design, ARM core-based SoC integration, and deep Verilog/VHDL knowledge. You will work on AMBA protocols (AXI/AHB/APB), Lint/CDC analysis, and FPGA prototyping to accelerate development.

The role requires hands-on experience in ASIC synthesis, STA, and equivalence checking, collaborating with cross-functional teams to hit critical milestones and deliver robust designs.

Responsibilities

• Execute RTL design and coding to expert level.
• Integrate ARM-based designs into SoCs for full compatibility.
• Work with AMBA protocols: AXI, AHB, APB.
• Perform Lint and CDC analysis to ensure robustness.
• Utilize FPGA-based designs or prototyping for development.
• Apply Verilog/VHDL and ARM SoC architecture knowledge.
• Perform ASIC synthesis and Static Timing Analysis.
• Execute equivalence checking to verify design accuracy.
• Collaborate with cross-functional teams to meet milestones.
• Participate in debugging, provide insights, and share findings.

Skills

RTL design

ARM SoC integration

Verilog/VHDL

AMBA AXI/AHB/APB

Lint & CDC analysis

FPGA prototyping

ASIC synthesis

Equivalency checking

Job description

We are currently seeking a highly skilled RTL/ASIC Design Engineer to join our dynamic team. If you possess hands‑on experience and expert‑level knowledge in RTL design, SoC integration of ARM core‑based designs, and a deep understanding of Verilog/VHDL, we invite you to apply.

Responsibilities:

• Execute RTL design and coding with expert‑level proficiency
• Integrate ARM core‑based designs into SoCs, ensuring seamless compatibility
• Work with AMBA Bus protocols, including AXI, AHB, APB
• Conduct Lint and CDC analysis for design robustness
• Utilize FPGA‑based designs or FPGA prototyping for development
• Apply in‑depth knowledge of Verilog/VHDL and ARM SoC architecture
• Perform ASIC synthesis and Static Timing Analysis at an expert level
• Execute equivalency checking to ensure design accuracy
• Collaborate with cross‑functional teams to achieve project milestones
• Participate in debugging sessions, provide insights, and maintain effective