Digital ASIC Design Engineer II — RTL & SoC Impact

FHLB Des Moines; San Jose (CA); Hybrid; USD 70,000 - 143,000; Full time

Benefits offered by this job

Health benefits from day one

ESP P program with 2 year look back

Job summary

Microchip Technology Inc. in San Jose seeks an Engineer II to drive RTL implementation of digital IP blocks, focusing on power, performance, and area targets.

You will translate architectural concepts into SystemVerilog, work with SoC teams, and collaborate with Physical Design to resolve timing and routing challenges. The role requires 2.5–5 years in ASIC/FPGA digital design, a BS in Electrical Engineering, and proficiency in SystemVerilog and Cadence/Synopsys flows.

Qualifications

• 2.5–5 years of proven experience in ASIC or FPGA digital design.
• BS degree in Electrical Engineering.
• Proficiency in SystemVerilog and design techniques.
• Experience with front-end EDA flows (Cadence/Synopsys).
• Familiarity with PHY/Serdes protocols is a plus.

Responsibilities

• Follow the micro-architecture and implement RTL (SystemVerilog) of complex digital IP blocks from concept to delivery.
• Drive Power, Performance and Area trade-offs to meet targets.
• Collaborate with SoC teams to ensure seamless connectivity and timing.
• Lead Lint, CDC, RDC, and formal verification efforts.
• Record design activities and cooperate with Physical Design teams to close timing.

Skills

SystemVerilog

ASIC design

Post-silicon validation

Scripting for efficiency

Education

BS in Electrical Engineering

Tools

VCS

SpyGlass

Design Compiler

PrimeTime

Job description

Microchip Technology Inc. in San Jose seeks an Engineer II to drive RTL implementation of digital IP blocks, focusing on power, performance, and area targets.

You will translate architectural concepts into SystemVerilog, work with SoC teams, and collaborate with Physical Design to resolve timing and routing challenges. The role requires 2.5–5 years in ASIC/FPGA digital design, a BS in Electrical Engineering, and proficiency in SystemVerilog and Cadence/Synopsys flows.