Lead ASIC Physical Design Engineer - Mentor & Tape-out

I2Intech LLC; San Jose (CA); On-site; USD 200,000 - 260,000; Full time

Job summary

I2Intech LLC in San Jose, CA is seeking a Lead Physical Design Engineer to own the implementation flow for complex blocks and top-level integration. You will mentor a team of PD engineers and coordinate with RTL, DFT, STA and signoff teams to resolve cross-functional issues.

You will drive timing closure for high-speed designs, optimize PPA, and ensure tape-out schedules are met, with hands-on leadership across 16nm or below processes and FinFET experience.

Qualifications

• Bachelor's or Master's in Electrical Engineering required.
• 10+ years in physical design with multiple tape-outs at 16nm or below.
• Strong leadership and partner-facing communication skills.

Responsibilities

• Own floorplanning, placement, CTS, routing and timing closure for blocks and top level.
• Define and maintain the implementation flow and methodology across the team.
• Drive PPA optimisation and closure of timing, power, IR/EM and physical verification.
• Mentor and review the work of PD engineers; plan and track deliverables.
• Interface with RTL, DFT, STA and signoff teams to resolve cross-functional issues.

Skills

Physical design

Tape-out experience

Innovus

Fusion Compiler

ICC2

PrimeTime/Tempus

Calibre

Redhawk/Voltus

Tcl/Python scripting

Flow automation

Leadership

Partner-facing communication

Education

Bachelor's or Master's in Electrical Engineering

Tools

Innovus

Fusion Compiler/ICC2

PrimeTime/Tempus

Calibre

Redhawk/Voltus

Job description

I2Intech LLC in San Jose, CA is seeking a Lead Physical Design Engineer to own the implementation flow for complex blocks and top-level integration. You will mentor a team of PD engineers and coordinate with RTL, DFT, STA and signoff teams to resolve cross-functional issues.

You will drive timing closure for high-speed designs, optimize PPA, and ensure tape-out schedules are met, with hands-on leadership across 16nm or below processes and FinFET experience.