ASIC Design Engineer

I2Intech LLC; San Jose, Austin (CA, TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Flexible engagement models

Continuous upskilling

Job summary

I2Intech LLC in San Jose, CA is seeking an experienced RTL designer to translate architectures into synthesizable SystemVerilog for ASIC/SoC projects.

You will define micro-architecture, collaborate with DV/DFT/PD teams, and ensure timing closure, low-power design, and tape-out readiness.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering.
• Proven RTL design experience on ASIC or SoC projects.
• Experience with bus protocols such as AXI, AHB, APB.

Responsibilities

• Define micro-architecture and write detailed design specifications.
• Develop high-quality, synthesizable RTL in SystemVerilog/Verilog.
• Integrate in-house and third-party IPs; manage SoC interconnect and memory maps.
• Run and clean Lint, CDC and RDC checks; author UPF for low-power designs.
• Support synthesis, timing closure and ECO activities.
• Collaborate with DV, DFT and PD teams to deliver tape-out ready designs.

Skills

RTL design experience

Digital design fundamentals

Clock domain crossing

Scripting: Python/Perl/Tcl

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

SpyGlass

Questa CDC

Synthesis flows

Job description

Design and integrate digital blocks and subsystems from specification through synthesis-ready, DFT-ready RTL.

ASIC Design San Jose, CA / Austin, TX (USA)

You will translate architectural requirements into robust, synthesizable RTL and integrate IPs into subsystem and SoC-level designs. The role spans micro-architecture definition, RTL coding, lint/CDC/RDC cleanliness, low‑power intent, and close collaboration with verification, DFT and physical design teams through tape‑out.

What you'll do

• Define micro‑architecture and write detailed design specifications.
• Develop high‑quality, synthesizable RTL in SystemVerilog/Verilog.
• Integrate in‑house and third‑party IPs; manage SoC interconnect and memory maps.
• Run and clean Lint, CDC and RDC checks; author UPF for low‑power designs.
• Support synthesis, timing closure and ECO activities.
• Collaborate with DV, DFT and PD teams to deliver tape‑out ready designs.

What you bring

• Bachelor's or Master's in Electrical/Computer Engineering.
• Proven RTL design experience on ASIC or SoC projects.
• Strong understanding of digital design fundamentals, timing and clock domain crossing.
• Familiarity with Lint/CDC tools (SpyGlass, Questa CDC) and synthesis flows.
• Experience with bus protocols such as AXI, AHB, APB.
• Scripting in Python, Perl or Tcl.

Nice to have

• Experience with low‑power design (UPF/CPF) and multi‑voltage domains.
• IP‑XACT based integration flows.
• Exposure to high‑speed interfaces or processor subsystems.

Why I2Intech

You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.