RTL Design Engineer II — ASIC/FPGA, High-Speed

Microchip Technology Inc.; Allentown (Lehigh County); On-site; USD 110,000 - 150,000; Full time

Job summary

Microchip Technology Inc. is seeking an RTL design engineer to design, simulate and verify RTL blocks for an SOC with diverse IP. You will work on imaging, networking, compute and data storage interfaces.

You will participate in RTL implementation, timing verification and test-chip porting, with FPGA experience a plus. A strong background in SystemVerilog, scripting, and Linux is required.

Qualifications

• 2–5 years of experience in RTL design for ASIC implementation.
• Bachelor’s degree in Electrical/Computer Engineering or Computer Science.
• Experience with RTL design tools including entry, synthesis, formal verification, RTL/gate level simulation.
• Proficiency in SystemVerilog; experience with Verilog simulation tools.
• Ability to design complex state machines and datapath logic.
• Proficiency in TCL/Perl/Python and Linux; knowledge of industry standards.
• Strong written and verbal communication; self-motivated team player.

Responsibilities

• General RTL and ASIC development.
• Detailed module design, performance analysis and design specification creation.
• Participate in RTL implementation, synthesis, simulation, pre-layout/post-layout timing verification.
• Understand high-speed design techniques to improve bandwidth and reduce latency.
• Support porting the design into test chips and emulation platforms; FPGA experience is advantageous.

Skills

RTL design

SystemVerilog

Scripting: TCL/Perl/Python

Linux

State machines & datapath

Communication skills

Education

Bachelor's in Electrical Engineering / Computer Engineering / Computer Science

Master's preferred

Tools

Design entry tools

Synthesis tools

Formal verification tools

Verilog/SystemVerilog simulators

Static timing analysis tools

Job description

Microchip Technology Inc. is seeking an RTL design engineer to design, simulate and verify RTL blocks for an SOC with diverse IP. You will work on imaging, networking, compute and data storage interfaces.

You will participate in RTL implementation, timing verification and test-chip porting, with FPGA experience a plus. A strong background in SystemVerilog, scripting, and Linux is required.