Design Engineer - ASIC/RTL

Infobahn Softworld Inc; San Jose (CA); Sur place; USD 150 000 - 230 000; Plein temps

Résumé du poste

Infobahn Softworld Inc is seeking a seasoned RTL/ASIC design engineer in the San Jose area to drive design for production tape-outs.

You will design RTL blocks for SOCs, integrate IP, and work with synthesis, STA, and optimization teams to meet timing, area, and power targets. Collaboration with architecture, verification, and physical design is essential.

Qualifications

• Proven track record of ASIC design on multiple production tape-outs.
• Experience designing RTL blocks for SOCs.
• Experience integrating ASIC IP into an SOC.
• Experience with synthesis, STA, and optimizations.

Responsabilités

• Write micro-architecture documentation and own major portions of design and implementation.
• Collaborate with architecture and hardware teams to understand the requirements.
• Work with verification and physical design teams to achieve high quality design and tape-out.
• Design and implement logic functions enabling efficient test and debug.
• Participate in silicon bring-up for features owned.
• Contribute in cross-functional teams to solve novel problems across multiple functional areas.
• Implement automation to increase design team efficiency.

Connaissances

ASIC design

RTL design

Tape-out experience

Synthesis

STA

Python scripting

Perl scripting

Tcl scripting

Outils

Arm architecture

APB protocol

AXI protocol

CHI protocol

Description du poste

- Experience in Designing RTL block for an SOC.

- Must have proven track record of ASIC design on several production tape-outs.

- Experience with Lint, CDC, RDC.

Experience:

• Must have proven track record of ASIC design on several production tape-outs.
• Experience in Designing RTL block for an SOC.
• Experience in integrating ASIC IP into an SOC.
• Experience with synthesis, static timing analysis & optimizations.

Nice-to-have:

• Experience writing timing constraints and exceptions.
• Experience with automation using scripting techniques such as PERL, Python or Tcl
• Experience in Power-saving techniques.
• Experience with Arm architecture and APB, AXI, CHI protocols.
• Experience with design involving Interconnects.
• Ability to develop clear and concise engineering documentation.
• Ability to organize and present complex technical information.
• Strong verbal and written communication skills

Responsibilities:

• Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
• Collaborate with architecture and hardware teams to understand the requirements.
• Work with verification and physical design teams to achieve high quality design and successful tape out.
• Design and implement logic functions that enable efficient test and debug.
• Participate in silicon bring-up for features owned.
• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
• Implement automation to increase design team efficiency