RISC-V Verification Engineer: Test Generator

Qualcomm; Cupertino (CA); On-site; USD 167,000 - 251,000; Full time

Job summary

Qualcomm Technologies, Inc. in Cupertino seeks a verification engineer to contribute to a Python-based random test generation framework and its assembler library for the RVA23.1 ISA, enabling a JIT-style simulator that exercises privileged modes, virtual memory, and vector extensions.

You will implement RISC-V extension generation objects, verify encodings, and craft constraint-driven test themes to boost RTL coverage while collaborating with ISS/RTL teams on failures.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Responsibilities

• Implement new generation objects for RISC-V extensions; common micro-architectural scenarios; and complex data/control-flow composable idioms.
• Add instruction forms and encodings to the python companion assembler and verifying bit-level correctness against the RISC-V ISA spec.
• Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
• Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
• Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic (register allocators, address-space managers, data fillers).

Skills

Python 3

RISC-V ISA

CSR semantics

Privilege levels

Memory model

Generator coroutines

OO design patterns

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master’s degree in Electrical/Computer Engineering or Computer Science

PhD in Electrical/Computer Engineering/Computer Science

Job description

Qualcomm Technologies, Inc. in Cupertino seeks a verification engineer to contribute to a Python-based random test generation framework and its assembler library for the RVA23.1 ISA, enabling a JIT-style simulator that exercises privileged modes, virtual memory, and vector extensions.

You will implement RISC-V extension generation objects, verify encodings, and craft constraint-driven test themes to boost RTL coverage while collaborating with ISS/RTL teams on failures.