Software Engineer — RISC-V Random Test Generator

Qualcomm; Cupertino (CA); On-site; USD 167,000 - 251,000; Full time

Job summary

Qualcomm Technologies, Inc. in Cupertino seeks a verification engineer to contribute to a Python-based random test generation framework and its assembler library for the RVA23.1 ISA, enabling a JIT-style simulator that exercises privileged modes, virtual memory, and vector extensions.

You will implement RISC-V extension generation objects, verify encodings, and craft constraint-driven test themes to boost RTL coverage while collaborating with ISS/RTL teams on failures.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Responsibilities

• Implement new generation objects for RISC-V extensions; common micro-architectural scenarios; and complex data/control-flow composable idioms.
• Add instruction forms and encodings to the python companion assembler and verifying bit-level correctness against the RISC-V ISA spec.
• Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
• Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
• Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic (register allocators, address-space managers, data fillers).

Skills

Python 3

RISC-V ISA

CSR semantics

Privilege levels

Memory model

Generator coroutines

OO design patterns

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master’s degree in Electrical/Computer Engineering or Computer Science

PhD in Electrical/Computer Engineering/Computer Science

Job description

Qualcomm Technologies, Inc.

Job Area: Engineering Group, Engineering Group > CPU Engineering

General Summary

About the Role You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain. The RTG drives a JIT-style, simulator- coupled generator that produces ELF binaries exercising the RVA23.1 ISA - including privileged modes, virtual memory, interrupts, vector, and cryptography extensions. The assembler library provides the bit-accurate instruction encoding layer that the RTG and other tools consume.

What You’ll Do

• Implement new generation objects for RISC-V extensions; common micro-architectural scenarios; and complex data/control-flow composable idioms.
• Add instruction forms and encodings to the python companion assembler and verifying bit-level correctness against the RISC-V ISA spec.
• Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
• Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
• Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic (register allocators, address-space managers, data fillers).

What We’re Looking For

• 2-5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
• Solid Python 3 skills; comfort with generator-based coroutines and object- oriented design patterns.
• Working knowledge of the RISC-V ISA: instruction encoding formats (R/I/S/B/ U/J, compressed, vector), CSR semantics, privilege levels (M/S/U), and the memory model. Alternatively, similar knowledge for x86 or ARM.
• Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.
• Exposure to random test generation flows or ISS/RTL co-simulation is a plus.

Nice to Have

• Compiler development experience.
• Understanding of hypervisor and/or AIA/IMSIC interrupt architecture.
• Familiarity with constraint-propagation libraries.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Pay range and Other Compensation & Benefits

$167,100.00 - $250,700.00

Pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

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