RISC-V CPU Verification Engineer – Remote

Tenstorrent; Santa Clara (CA); On-site; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Mid Core Design Verification Engineer to verify the next generation of high-performance RISC-V CPU cores. You will collaborate with CPU architects, RTL designers, and software engineers to develop verification strategies, build test benches, and drive issues to closure.

This hands-on role offers ownership of verification tasks, including test plan development, constrained-random testing, and functional coverage, with a focus on out-of-order pipelines and caches.

Qualifications

• 6+ years of design verification experience for CPUs, SoCs, or ASICs.
• Strong SystemVerilog and UVM experience with testbenches and coverage.
• Understanding of pipelines, out-of-order execution, caches, and scheduling.
• Experience debugging RTL using waveforms and sim tools.
• Strong C/C++ or Python skills working with RTL teams.

Responsibilities

• Own verification tasks from test plans to test bench architecture.
• Develop robust test environments and coverage plans.
• Debug failures and drive issues to closure with RTL teams.
• Collaborate with CPU architects and RTL designers.
• Verify next-gen high-performance RISC-V cores.

Skills

SystemVerilog

UVM

Testbench development

Constrained-random testing

Assertions

Functional coverage

C/C++ skills

Python skills

RTL debugging

CPU architecture

Job description

Tenstorrent is seeking a Mid Core Design Verification Engineer to verify the next generation of high-performance RISC-V CPU cores. You will collaborate with CPU architects, RTL designers, and software engineers to develop verification strategies, build test benches, and drive issues to closure.

This hands-on role offers ownership of verification tasks, including test plan development, constrained-random testing, and functional coverage, with a focus on out-of-order pipelines and caches.