RISC-V Verification Engineer: Random Test Generator & Assembler

Qualcomm; Cupertino (CA); On-site; USD 167,000 - 251,000; Full time

Job summary

Qualcomm Technologies, Inc. in California is seeking a software/hardware engineer to contribute to a Python-based random test generation framework and an assembler library that drive a RISC-V CPU design-verification toolchain.

The RTG generates JIT-style, simulator-coupled test cases exercising the RVA23.1 ISA, including privileged modes, memory, interrupts and cryptography extensions. You will implement new generation objects for RISC-V extensions, verify encodings, and write themes to improve

Qualifications

• 2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
• Solid Python 3 skills and object-oriented design patterns.
• Working knowledge of RISC-V ISA instruction encodings, privilege levels, and memory models.
• Familiarity with virtual memory and IMSIC/interrupt handling is a plus.

Responsibilities

• Implement new generation objects for RISC-V extensions and complex data/control-flow idioms.
• Add instruction forms and encodings to the assembler and verify bit-level correctness.
• Write and tune generation themes to improve RTL coverage.
• Collaborate with ISS/RTL verification engineers to triage failures and add regression scenarios.
• Triage exceptions, page-table builders, and interrupt handling with the privileged software stack.

Skills

Python 3

CPU design verification

RISC-V ISA knowledge

Hardware-software co-design

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's degree in Electrical Engineering, Computer Engineering, Computer Science

PhD in Electrical Engineering, Computer Engineering, Computer Science

Tools

Python-based RTG framework

Assembler library

Constraint-propagation libraries

ISS/RTL co-simulation

Job description

Qualcomm Technologies, Inc. in California is seeking a software/hardware engineer to contribute to a Python-based random test generation framework and an assembler library that drive a RISC-V CPU design-verification toolchain.

The RTG generates JIT-style, simulator-coupled test cases exercising the RVA23.1 ISA, including privileged modes, memory, interrupts and cryptography extensions. You will implement new generation objects for RISC-V extensions, verify encodings, and write themes to improve