RISC-V Front-End Verification Engineer

Tenstorrent; Town of Texas, Northern (WI, KY); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Design Verification Engineer to contribute to unit-level front-end DV for our RISC-V CPU. You will build testbenches, generate stimulus, and develop checkers for instruction fetch, branch predictors, and related structures.

This hybrid role is based in Austin, TX or Santa Clara, CA, with offers aligned to experience. You will collaborate with RTL, performance modeling, and software teams to ensure robust verification across cycles and transaction-level checking.

Qualifications

• Experience verifying CPU front-end blocks using SystemVerilog, UVM, and C++.
• Hands-on testbench construction with precise stimulus and checkers.
• Ability to build reusable DV components like transactors and scoreboards.

Responsibilities

• Build and maintain UVM testbenches for instruction fetch units and branch predictors.
• Develop constrained-random and directed tests targeting fetch and cache interactions.
• Integrate C++ reference models into the verification framework.
• Track coverage and drive closure of functional and code coverage goals.

Skills

SystemVerilog

UVM

C++

Testbench development

Front-end verification

Tools

Verilator

UVM framework

Job description

Tenstorrent is seeking a Design Verification Engineer to contribute to unit-level front-end DV for our RISC-V CPU. You will build testbenches, generate stimulus, and develop checkers for instruction fetch, branch predictors, and related structures.

This hybrid role is based in Austin, TX or Santa Clara, CA, with offers aligned to experience. You will collaborate with RTL, performance modeling, and software teams to ensure robust verification across cycles and transaction-level checking.