Software Engineer — RISC-V Random Test Generator & Assembler Infrastructure

Qualcomm; Cupertino (CA); On-site; USD 167,000 - 251,000; Full time

Job summary

Qualcomm Technologies, Inc. in California is seeking a software/hardware engineer to contribute to a Python-based random test generation framework and an assembler library that drive a RISC-V CPU design-verification toolchain.

The RTG generates JIT-style, simulator-coupled test cases exercising the RVA23.1 ISA, including privileged modes, memory, interrupts and cryptography extensions. You will implement new generation objects for RISC-V extensions, verify encodings, and write themes to improve

Qualifications

• 2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
• Solid Python 3 skills and object-oriented design patterns.
• Working knowledge of RISC-V ISA instruction encodings, privilege levels, and memory models.
• Familiarity with virtual memory and IMSIC/interrupt handling is a plus.

Responsibilities

• Implement new generation objects for RISC-V extensions and complex data/control-flow idioms.
• Add instruction forms and encodings to the assembler and verify bit-level correctness.
• Write and tune generation themes to improve RTL coverage.
• Collaborate with ISS/RTL verification engineers to triage failures and add regression scenarios.
• Triage exceptions, page-table builders, and interrupt handling with the privileged software stack.

Skills

Python 3

CPU design verification

RISC-V ISA knowledge

Hardware-software co-design

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's degree in Electrical Engineering, Computer Engineering, Computer Science

PhD in Electrical Engineering, Computer Engineering, Computer Science

Tools

Python-based RTG framework

Assembler library

Constraint-propagation libraries

ISS/RTL co-simulation

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > CPU Engineering

General Summary

About the Role

You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain. The RTG drives a JIT-style, simulator- coupled generator that produces ELF binaries exercising the RVA23.1 ISA — including privileged modes, virtual memory, interrupts, vector, and cryptography extensions. The assembler library provides the bit-accurate instruction encoding

layer that the RTG and other tools consume.

What You'll Do

• Implement new generation objects for RISC-V extensions; common micro-architectural scenarios; and complex data/control-flow composable idioms.
• Add instruction forms and encodings to the python companion assembler and verifying bit-level correctness against the RISC-V ISA spec.
• Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
• Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
• Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic (register allocators, address-space managers, data fillers).
  
  
  

What We're Looking For

• 2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
• Solid Python 3 skills; comfort with generator-based coroutines and object- oriented design patterns.
• Working knowledge of the RISC-V ISA: instruction encoding formats (R/I/S/B/ U/J, compressed, vector), CSR semantics, privilege levels (M/S/U), and the memory model. Alternatively, similar knowledge for x86 or ARM.
• Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.
• Exposure to random test generation flows or ISS/RTL co-simulation is a plus.
  
  
  

Nice to Have

• Compiler development experience.
• Understanding of hypervisor and/or AIA/IMSIC interrupt architecture.
• Familiarity with constraint-propagation libraries.
  
  
  

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
  
  
  

OR

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

OR

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

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Pay Range And Other Compensation & Benefits

$167,100.00 - $250,700.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.