RISC-V Verification Engineer - Python & ISA Tooling

Qualcomm; Cupertino, Northern (CA, KY); Hybrid; USD 167,000 - 251,000; Full time

Job summary

Qualcomm is seeking a CPU-design verification engineer to contribute to a Python-based random test generation framework and its assembler library, powering a RISC-V ISA verification toolchain. You will help drive a JIT-style generator producing ELF binaries for the RVA23.1 ISA, including privileged modes, virtual memory, and interrupts.

You will work with ISS and RTL teams to triage failures, craft regression scenarios, and refine constraint logic across register allocation and address-space

Qualifications

• Bachelor’s degree required with 4+ years in Hardware/Software engineering or related.
• Master’s degree with 3+ years; PhD with 2+ years.
• Strong Python 3 skills and OO design patterns.

Responsibilities

• Implement new generation objects for RISC-V extensions and complex data/control-flow idioms.
• Add instruction forms and encodings to the python counterpart assembler.
• Write and tune generation themes to improve RTL coverage.
• Triage failures with ISS/RTL engineers and adjust constraint logic.

Skills

Python programming

CPU design verification

ISS development

Object-oriented design

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master’s degree in Electrical Engineering, Computer Engineering, or related field

PhD in Electrical Engineering, Computer Engineering, or related field

Tools

RISC-V ISA formats

Sv39/Sv48 memory models

PMP configuration knowledge

Job description

Qualcomm is seeking a CPU-design verification engineer to contribute to a Python-based random test generation framework and its assembler library, powering a RISC-V ISA verification toolchain. You will help drive a JIT-style generator producing ELF binaries for the RVA23.1 ISA, including privileged modes, virtual memory, and interrupts.

You will work with ISS and RTL teams to triage failures, craft regression scenarios, and refine constraint logic across register allocation and address-space